/*
 * Mediatek's MT6768 SoC device tree source
 *
 * Copyright (C) 2018 MediaTek Inc.
 * Copyright (C) 2021 XiaoMi, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See http://www.gnu.org/licenses/gpl-2.0.html for more details.
 */

/dts-v1/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/mmc/mt6768-msdc.h>
#include <dt-bindings/memory/mt6768-larb-port.h>
#include <dt-bindings/pinctrl/mt6768-pinfunc.h>
#include <dt-bindings/gce/mt6768-gce.h>
#include <dt-bindings/clock/mt6768-clk.h>
#include <dt-bindings/iio/mt635x-auxadc.h>
#include <dt-bindings/mfd/mt6358-irq.h>
#include <dt-bindings/gce/mt6768-gce.h>
#include <generated/autoconf.h>

/ {
	model = "MT6768";
	compatible = "mediatek,MT6768";
	interrupt-parent = <&sysirq>;
	#address-cells = <2>;
	#size-cells = <2>;

	/* chosen */
	chosen: chosen {
		bootargs = "console=tty0 console=ttyS0,921600n1 root=/dev/ram \
vmalloc=400M slub_debug=OFZPU swiotlb=noforce \
cgroup.memory=nosocket,nokmem \
firmware_class.path=/vendor/firmware \
page_owner=on loop.max_part=7";
		kaslr-seed = <0 0>;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@000 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0000>;
			enable-method = "psci";
			clock-frequency = <1701000000>;
			cpu-idle-states = <&STANDBY &MCDI_CPU &MCDI_CLUSTER>,
				<&idledram &idlesyspll &idlebus26m &SUSPEND>;
		};

		cpu1: cpu@001 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0100>;
			enable-method = "psci";
			clock-frequency = <1701000000>;
			cpu-idle-states = <&STANDBY &MCDI_CPU &MCDI_CLUSTER>,
				<&idledram &idlesyspll &idlebus26m &SUSPEND>;
		};

		cpu2: cpu@002 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0200>;
			enable-method = "psci";
			clock-frequency = <1701000000>;
			cpu-idle-states = <&STANDBY &MCDI_CPU &MCDI_CLUSTER>,
				<&idledram &idlesyspll &idlebus26m &SUSPEND>;
		};

		cpu3: cpu@003 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0300>;
			enable-method = "psci";
			clock-frequency = <1701000000>;
			cpu-idle-states = <&STANDBY &MCDI_CPU &MCDI_CLUSTER>,
				<&idledram &idlesyspll &idlebus26m &SUSPEND>;
		};

		cpu4: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0400>;
			enable-method = "psci";
			clock-frequency = <1701000000>;
			cpu-idle-states = <&STANDBY &MCDI_CPU &MCDI_CLUSTER>,
				<&idledram &idlesyspll &idlebus26m &SUSPEND>;
		};

		cpu5: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0500>;
			enable-method = "psci";
			clock-frequency = <1701000000>;
			cpu-idle-states = <&STANDBY &MCDI_CPU &MCDI_CLUSTER>,
				<&idledram &idlesyspll &idlebus26m &SUSPEND>;
		};

		cpu6: cpu@102 {
			device_type = "cpu";
			compatible = "arm,cortex-a75";
			reg = <0x0600>;
			enable-method = "psci";
			clock-frequency = <2171000000>;
			cpu-idle-states = <&STANDBY &MCDI_CPU &MCDI_CLUSTER>,
				<&idledram &idlesyspll &idlebus26m &SUSPEND>;
		};

		cpu7: cpu@103 {
			device_type = "cpu";
			compatible = "arm,cortex-a75";
			reg = <0x0700>;
			enable-method = "psci";
			clock-frequency = <2171000000>;
			cpu-idle-states = <&STANDBY &MCDI_CPU &MCDI_CLUSTER>,
				<&idledram &idlesyspll &idlebus26m &SUSPEND>;
		};


		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
				core2 {
					cpu = <&cpu2>;
				};
				core3 {
					cpu = <&cpu3>;
				};
				core4 {
					cpu = <&cpu4>;
				};
				core5 {
					cpu = <&cpu5>;
				};
				doe_dvfs_cl0: doe {
				};
			};
			cluster1 {
				core0 {
					cpu = <&cpu6>;
				};
				core1 {
					cpu = <&cpu7>;
				};
				doe_dvfs_cl1: doe {
				};

			};

		};

		idle-states {
			entry-method = "arm,psci";

			STANDBY: standby {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x00000001>;
				entry-latency-us = <600>;
				exit-latency-us = <600>;
				min-residency-us = <1200>;
			};

			MCDI_CPU: mcdi-cpu {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x00010001>;
				entry-latency-us = <600>;
				exit-latency-us = <600>;
				min-residency-us = <1200>;
			};

			MCDI_CLUSTER: mcdi-cluster {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x01010001>;
				entry-latency-us = <600>;
				exit-latency-us = <600>;
				min-residency-us = <1200>;
			};

			idledram: idledram {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x01010002>;
				entry-latency-us = <800>;
				exit-latency-us = <1000>;
				min-residency-us = <2000>;
				status = "okay";
			};

			idlesyspll: idlesyspll {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x01010003>;
				entry-latency-us = <800>;
				exit-latency-us = <1000>;
				min-residency-us = <2000>;
				status = "okay";
			};

			idlebus26m: idlebus26m {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x01010004>;
				entry-latency-us = <800>;
				exit-latency-us = <1000>;
				min-residency-us = <2000>;
				status = "okay";
			};

			SUSPEND: suspend {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x01010005>;
				entry-latency-us = <800>;
				exit-latency-us = <1000>;
				min-residency-us = <2000>;
			};
		};
	};

	cache_parity {
		compatible = "mediatek,cache_parity";
		version = <1>;
		reg = <0 0x0c530000 0 0x10000>;
		err_level = <1>;
		irq_config = <0 0x8090 0x0000ff00 0x8090 68 0x8090 0x000000ff>,
			<1 0x8090 0x0000ff00 0x8090 68 0x8090 0x000000ff>,
			<2 0x8090 0x0000ff00 0x8090 68 0x8090 0x000000ff>,
			<3 0x8090 0x0000ff00 0x8090 68 0x8090 0x000000ff>,
			<4 0x8090 0x0000ff00 0x8090 68 0x8090 0x000000ff>,
			<5 0x8090 0x0000ff00 0x8090 68 0x8090 0x000000ff>,
			<6 0x8090 0x0000ff00 0x8090 68 0x8090 0x000000ff>,
			<7 0x8090 0x0000ff00 0x8090 68 0x8090 0x000000ff>,
			<1024 0xc8c0 0x01000000 0xc8c0 12 0xc8c8 0x00000001>;
		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	};

	memory {
		device_type = "memory";
		reg = <0 0x40000000 0 0x3e605000>;
	};

	psci {
		compatible      = "arm,psci-1.0";
		method          = "smc";
	};

	/* Trustonic Mobicore SW IRQ number 329 = 32 + 297 */
	mobicore {
		compatible = "trustonic,mobicore";
		interrupts = <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>;
	};

	tee_sanity {
		compatible = "mediatek,tee_sanity";
		interrupts = <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>;
	};

	/* Microtrust SW IRQ number 299(331) ~ 304(336) */
	utos {
		compatible = "microtrust,utos";
		interrupts = <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 300 IRQ_TYPE_EDGE_RISING>;
	};
	utos_tester {
		compatible = "microtrust,tester-v1";
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
	};

	dsu-pmu-0 {
		compatible = "arm,dsu-pmu";
		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
		cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
			<&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
	};

	reserved_memory: reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		zmc-default {
			compatible = "mediatek,zone_movable_cma";
			size = <0 0x2d000000>;
			alignment = <0 0x1000000>;
			alloc-ranges = <0 0xc0000000 4 0x00000000>;
		};

		reserve-memory-sspm_share {
			compatible = "mediatek,reserve-memory-sspm_share";
			no-map;
			status = "okay";
#if defined(CONFIG_MTK_GMO_RAM_OPTIMIZE) || defined(CONFIG_MTK_MET_MEM_ALLOC)
			size = <0 0x110000>; /* 1M + 64K */
#else
			size = <0 0x510000>; /* 5M + 64K */
#endif
			alignment = <0 0x10000>;
			alloc-ranges = <0 0x40000000 0 0x60000000>;
		};

		reserve-memory-scp_share {
			compatible = "mediatek,reserve-memory-scp_share";
			no-map;
			size = <0 0x00300000>;
			alignment = <0 0x1000000>;
			alloc-ranges = <0 0x40000000 0 0x50000000>;
		};

		ion-carveout-heap {
			compatible = "mediatek,ion-carveout-heap";
			no-map;
			size = <0 0x9000>;
			alignment = <0 0x1000>;
			alloc-ranges = <0 0xc0000000 4 0x00000000>;
		};

		consys-reserve-memory {
			compatible = "mediatek,consys-reserve-memory";
			no-map;
			size = <0 0x400000>;
			alignment = <0 0x1000000>;
			alloc-ranges = <0 0x40000000 0 0x80000000>;
		};

		wifi_mem: wifi-reserve-memory {
			compatible = "shared-dma-pool";
			no-map;
			size = <0 0x300000>;
			alignment = <0 0x1000000>;
			alloc-ranges = <0 0x40000000 0 0x80000000>;
		};

#ifdef CONFIG_MICROTRUST_TEE_SUPPORT
		soter-shared-mem {
			compatible = "microtrust,shared_mem";
			no-map;
#if defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT) || \
	defined(CONFIG_MTK_CAM_SECURITY_SUPPORT)
			size = <0 0xc00000>;
			alignment = <0 0x1000000>;
#else
			size = <0 0x200000>;
			alignment = <0 0x200000>;
#endif
			alloc-ranges = <0 0x40000000 0 0x50000000>;
		};
#endif
	};

	cpu_dbgapb: cpu_dbgapb@0e010000 {
		compatible = "mediatek,hw_dbg";
		num = <8>;
		reg =	<0 0x0e010000 0 0x1000>,
			<0 0x0e110000 0 0x1000>,
			<0 0x0e210000 0 0x1000>,
			<0 0x0e310000 0 0x1000>,
			<0 0x0e410000 0 0x1000>,
			<0 0x0e510000 0 0x1000>,
			<0 0x0e610000 0 0x1000>,
			<0 0x0e710000 0 0x1000>;
	};

	gic: interrupt-controller {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		#address-cells = <2>;
		#size-cells = <2>;
		#redistributor-regions = <1>;
		interrupt-parent = <&gic>;
		interrupt-controller;
		reg = <0 0x0c000000 0 0x40000>, // distributor
		      <0 0x0c040000 0 0x200000>, // redistributor
		      <0 0x0c53a650 0 0x50>; //INTPOL
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
	};

	sysirq: intpol-controller@0 {
		compatible = "mediatek,mt6577-sysirq";
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		reg = <0 0x0c53a650 0 0x50>;
	};

	chipid@08000000 {
		compatible = "mediatek,chipid";
		reg = <0 0x08000000 0 0x0004>,
		      <0 0x08000004 0 0x0004>,
		      <0 0x08000008 0 0x0004>,
		      <0 0x0800000c 0 0x0004>;
	};

	timer: timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
				<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
				<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
				<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
		clock-frequency = <13000000>;
	};

	infracfg_ao: infracfg_ao@10001000 {
		compatible = "mediatek,infracfg_ao", "syscon";
		reg = <0 0x10001000 0 0x1000>;
		interrupts = <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>;
		#clock-cells = <1>;
	};

	scpsys: scpsys@10001000 {
		compatible = "mediatek,scpsys", "syscon";
		reg =   <0 0x10001000 0 0x1000>, /* infra_ao */
			<0 0x10006000 0 0x1000>, /* spm */
			<0 0x14002000 0 0x1000>, /* spi_common */
			<0 0x1020e000 0 0x1000>, /* infracfg */
			<0 0x18004000 0 0x1000>, /* connsys */
			<0 0x18002000 0 0x1000>, /* connsys mcu */
			<0 0x10000000 0 0x1000>, /* ckgen */
			<0 0x16000000 0 0x1000>, /* vdec_gcon */
			<0 0x16025000 0 0x1000>; /* vdec */
		#clock-cells = <1>;
	};

	mcdi:mcdi@0010fc00 {
		compatible = "mediatek,mt6768-mcdi";
		mediatek,enabled = <1>;
		reg = <0 0x0010fc00 0 0x800>,
		      <0 0x0c53a000 0 0x1000>;
	};

	scp@10500000 {
		compatible = "mediatek,scp";
		status = "okay";
		reg = <0 0x10500000 0 0x80000>,
				<0 0x105c0000 0 0x3000>,
				<0 0x105c4000 0 0x1000>,
				<0 0x105d4000 0 0x6000>;
		interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
		core_1 = "enable";
		scp_sramSize = <0x00080000>;
	};

	scp_dvfs {
		compatible = "mediatek,scp_dvfs";
		clocks = <&topckgen CLK_TOP_SCP_SEL>,
			<&clk26m>,
			<&topckgen CLK_TOP_SYSPLL4_D2>,
			<&topckgen CLK_TOP_UNIVPLL2_D2>,
			<&topckgen CLK_TOP_SYSPLL1_D2>,
			<&topckgen CLK_TOP_UNIVPLL1_D2>,
			<&topckgen CLK_TOP_SYSPLL_D3>,
			<&topckgen CLK_TOP_UNIVPLL_D3>;

		clock-names = "clk_mux",
			"clk_pll_0",
			"clk_pll_1",
			"clk_pll_2",
			"clk_pll_3",
			"clk_pll_4",
			"clk_pll_5",
			"clk_pll_6";
	};

	topckgen: topckgen@10000000 {
		compatible = "mediatek,topckgen", "syscon";
		reg = <0 0x10000000 0 0x1000>;
		#clock-cells = <1>;
	};

	io_cfg_lt: io_cfg_lt@10002000 {
		compatible = "mediatek,io_cfg_lt";
		reg = <0 0x10002000 0 0x200>;
	};

	io_cfg_lm: io_cfg_lm@10002200 {
		compatible = "mediatek,io_cfg_lm";
		reg = <0 0x10002200 0 0x200>;
	};

	io_cfg_lb: io_cfg_lb@10002400 {
		compatible = "mediatek,io_cfg_lb";
		reg = <0 0x10002400 0 0x200>;
	};

	io_cfg_bl: io_cfg_bl@10002600 {
		compatible = "mediatek,io_cfg_bl";
		reg = <0 0x10002600 0 0x200>;
	};

	io_cfg_rm: io_cfg_rm@10002800 {
		compatible = "mediatek,io_cfg_rm";
		reg = <0 0x10002800 0 0x200>;
	};

	io_cfg_rb: io_cfg_rb@10002a00 {
		compatible = "mediatek,io_cfg_rb";
		reg = <0 0x10002a00 0 0x200>;
	};

	io_cfg_rt: io_cfg_rt@10002c00 {
		compatible = "mediatek,io_cfg_rt";
		reg = <0 0x10002c00 0 0x200>;
	};

	io_cfg_tl: io_cfg_tl@10002e00 {
		compatible = "mediatek,io_cfg_tl";
		reg = <0 0x10002e00 0 0x200>;
	};

	pericfg: pericfg@10003000 {
		compatible = "mediatek,pericfg", "syscon";
		reg = <0 0x10003000 0 0x1000>;
		#clock-cells = <1>;
	};

	efuse_dbg@10004000 {
		compatible = "mediatek,efuse_dbg";
		reg = <0 0x10004000 0 0x1000>;
	};

	gpio: gpio@10005000 {
		compatible = "mediatek,gpio";
		reg = <0 0x10005000 0 0x1000>;
	};

	pio: pinctrl {
		compatible = "mediatek,mt6768-pinctrl";
		reg_bases = <&gpio>,
			    <&io_cfg_lt>,
			    <&io_cfg_lm>,
			    <&io_cfg_lb>,
			    <&io_cfg_bl>,
			    <&io_cfg_rm>,
			    <&io_cfg_rb>,
			    <&io_cfg_rt>,
			    <&io_cfg_tl>;
		reg_base_eint = <&eint>;
		pins-are-numbered;
		gpio-controller;
		gpio-ranges = <&pio 0 0 186>;
		#gpio-cells = <2>;
		interrupt-controller;
		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
		#interrupt-cells = <4>;
	};

	sleep:sleep@10006000 {
		compatible = "mediatek,sleep";
		reg = <0 0x10006000 0 0x1000>;
		interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
	};

	toprgu:toprgu@10007000 {
		compatible = "mediatek,toprgu";
		reg = <0 0x10007000 0 0x1000>;
		interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW>;
	};

	clocks {
		clk26m: clk26m {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <26000000>;
		};

		clk32k: clk32k {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32000>;
		};
	};

	dcm: dcm {
		compatible = "mediatek,dcm";
	};

	apxgpt@10008000 {
		compatible = "mediatek,apxgpt";
		reg = <0 0x10008000 0 0x1000>;
		interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
		clocks =
			<&clk32k>;
	};

	hacc@1000a000 {
		compatible = "mediatek,hacc";
		reg = <0 0x1000a000 0 0x1000>;
		interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW>;
	};

	eint: apirq@1000b000 {
		compatible = "mediatek,apirq";
		reg = <0 0x1000b000 0 0x1000>;
		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
	};

	apmixed: apmixed@1000c000 {
		compatible = "mediatek,apmixed", "syscon";
		reg = <0 0x1000c000 0 0x1000>;
		#clock-cells = <1>;
	};

	fhctl@1000ce00 {
		compatible = "mediatek,fhctl";
		reg = <0 0x1000ce00 0 0x200>;
	};

	pwrap: pwrap@1000d000 {
		compatible = "mediatek,mt6768-pwrap";
		reg = <0 0x1000d000 0 0x1000>;
		reg-names = "pwrap";
		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk26m>, <&clk26m>;
		clock-names = "spi", "wrap";

		main_pmic: mt6358-pmic {
			compatible = "mediatek,mt6358-pmic";
			interrupt-parent = <&pio>;
			interrupts = <144 IRQ_TYPE_LEVEL_HIGH 144 0>;
			status = "okay";
		};

	};

	pwraph: pwraphal@ {
		compatible = "mediatek,pwraph";
		mediatek,pwrap-regmap = <&pwrap>;
	};

	pwrap_mpu@1000d000 {
		compatible = "mediatek,pwrap_mpu";
		reg = <0 0x1000d000 0 0x1000>;
	};

	pwrap_p2p@1005cb000 {
		compatible = "mediatek,pwrap_p2p";
		reg = <0 0x105cb000 0 0x1000>;
	};

	pwrap_md32@10448000 {
		compatible = "mediatek,pwrap_md32";
		reg = <0 0x10448000 0 0x1000>;
	};

	sleep_reg_md@1000f000 {
		compatible = "mediatek,sleep_reg_md";
		reg = <0 0x1000f000 0 0x1000>;
	};

	keypad: kp@10010000 {
		compatible = "mediatek,kp";
		reg = <0 0x10010000 0 0x1000>;
		interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_FALLING>;
	};

	mrdump_ext_rst: mrdump_ext_rst {
		compatible = "mediatek, mrdump_ext_rst-eint";
		mode = "IRQ";
		status = "okay";
	};

	topmisc@10011000 {
		compatible = "mediatek,topmisc";
		reg = <0 0x10011000 0 0x1000>;
	};

	dvfsrc: dvfsrc@10012000 {
		compatible = "mediatek,dvfsrc";
		reg = <0 0x10012000 0 0x1000>,
			<0 0x00110780 0 0x80>;
	};

	mbist_ao@10013000 {
		compatible = "mediatek,mbist_ao";
		reg = <0 0x10013000 0 0x1000>;
	};

	apcldmain_ao@10014000 {
		compatible = "mediatek,apcldmain_ao";
		reg = <0 0x10014000 0 0x400>;
	};

	apcldmaout_ao@10014400 {
		compatible = "mediatek,apcldmaout_ao";
		reg = <0 0x10014400 0 0x400>;
	};

	apcldmamisc_ao@10014800 {
		compatible = "mediatek,apcldmamisc_ao";
		reg = <0 0x10014800 0 0x400>;
	};

	apcldmamisc_ao@10014c00 {
		compatible = "mediatek,apcldmamisc_ao";
		reg = <0 0x10014c00 0 0x400>;
	};

	ddrphy@10015000 {
		compatible = "mediatek,ddrphy";
		reg = <0 0x10015000 0 0x1000>;
	};

	aes_top0@10016000 {
		compatible = "mediatek,aes_top0";
		reg = <0 0x10016000 0 0x1000>;
	};

	sys_timer@10017000 {
		compatible = "mediatek,sys_timer";
		reg = <0 0x10017000 0 0x1000>;
		reg-names = "sys_timer_base";
		interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&topckgen CLK_TOP_CLK13M>;
	};

	modem_temp_share@10018000 {
		compatible = "mediatek,modem_temp_share";
		reg = <0 0x10018000 0 0x1000>;
	};

	security_ao@1001a000 {
		compatible = "mediatek,security_ao";
		reg = <0 0x1001a000 0 0x1000>;
	};

	topckgen_ao@1001b000 {
		compatible = "mediatek,topckgen_ao";
		reg = <0 0x1001b000 0 0x1000>;
	};

	iocfg_0@10002000 {
		compatible = "mediatek,iocfg_0";
		reg = <0 0x10002000 0 0x200>;
	};

	iocfg_1@10002200 {
		compatible = "mediatek,iocfg_1";
		reg = <0 0x10002200 0 0x200>;
	};

	iocfg_2@10002400 {
		compatible = "mediatek,iocfg_2";
		reg = <0 0x10002400 0 0x200>;
	};

	iocfg_3@10002600 {
		compatible = "mediatek,iocfg_3";
		reg = <0 0x10002600 0 0x200>;
	};

	iocfg_4@10002800 {
		compatible = "mediatek,iocfg_4";
		reg = <0 0x10002800 0 0x200>;
	};

	iocfg_5@10002a00 {
		compatible = "mediatek,iocfg_5";
		reg = <0 0x10002a00 0 0x200>;
	};

	mdcldmain_ao@10015000 {
		compatible = "mediatek,mdcldmain_ao";
		reg = <0 0x10015000 0 0x400>;
	};

	mdcldmaout_ao@10015400 {
		compatible = "mediatek,mdcldmaout_ao";
		reg = <0 0x10015400 0 0x400>;
	};

	mdcldmamisc_ao@10015800 {
		compatible = "mediatek,mdcldmamisc_ao";
		reg = <0 0x10015800 0 0x400>;
	};

	sys_cirq@10204000 {
		compatible = "mediatek,sys_cirq";
		reg = <0 0x10204000 0 0x1000>;
		mediatek,cirq_num = <232>;
		mediatek,spi_start_offset = <64>;
		interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_LOW>;
	};

	mcucfg_mp0_counter@0c530000 {
		compatible = "mediatek,mcucfg_mp0_counter";
		reg = <0 0x0c530000 0 0x10000>;
	};

	mcucfg: mcucfg@0c530000 {
		compatible = "mediatek,mcucfg";
		reg = <0 0x0c530000 0 0x10000>;
	};

#ifdef CONFIG_MTK_IOMMU_V2
	iommu: m4u@10205000  {
		cell-index = <0>;
		compatible = "mediatek,iommu_v0";
		reg = <0 0x10205000 0 0x1000>;
		mediatek,larbs = <&smi_larb0 &smi_larb1 &smi_larb2>,
				<&smi_larb3 &smi_larb4>;
		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_LOW>;
		#iommu-cells = <1>;
	};
#endif
#ifdef CONFIG_MTK_M4U
	m4u@10205000 {
		cell-index = <0>;
		compatible = "mediatek,m4u";
		reg = <0 0x10205000 0 0x1000>;
		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_LOW>;
	};
#endif
	devapc@10207000 {
		compatible = "mediatek,mt6768-devapc";
		reg = <0 0x10207000 0 0x1000>,
		      <0 0x1000e000 0 0x1000>,
		      <0 0x10033000 0 0x1000>;
		interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infracfg_ao CLK_IFR_DEVICE_APC>;
		clock-names = "devapc-infra-clock";
	};

	hwrng: hwrng {
		compatible = "mediatek,mt67xx-rng";
	};

	bus_dbg@10208000 {
		compatible = "mediatek,bus_dbg-v2";
		reg = <0 0x10208000 0 0x1000>,
			  <0 0x10001000 0 0x1000>;
		mediatek,bus_dbg_con_offset = <0x2fc>;
		interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_LOW>;
	};

	ap_ccif0@10209000 {
		compatible = "mediatek,ap_ccif0";
		reg = <0 0x10209000 0 0x1000>;
		interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>;
	};

	md_ccif0@1020a000 {
		compatible = "mediatek,md_ccif0";
		reg = <0 0x1020a000 0 0x1000>;
	};

	ap_ccif1@1020b000 {
		compatible = "mediatek,ap_ccif1";
		reg = <0 0x1020b000 0 0x1000>;
		interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>;
	};

	md_ccif1@1020c000 {
		compatible = "mediatek,md_ccif1";
		reg = <0 0x1020c000 0 0x1000>;
	};

	infra_mbist@1020d000 {
		compatible = "mediatek,infra_mbist";
		reg = <0 0x1020d000 0 0x1000>;
	};

	infracfg@1020e000 {
		compatible = "mediatek,infracfg";
		reg = <0 0x1020e000 0 0x1000>;
	};

	trng@1020f000 {
		compatible = "mediatek,trng";
		reg = <0 0x1020f000 0 0x1000>;
		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>;
	};

	dxcc_sec@10210000 {
		compatible = "mediatek,dxcc_sec";
		reg = <0 0x10210000 0 0x1000>;
		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
	};

	mcupm_sram2@10211000 {
		compatible = "mediatek,mcupm_sram2";
		reg = <0 0x10211000 0 0x1000>;
	};

	cq_dma@10212000 {
		compatible = "mediatek,mt-cqdma-v1";
		reg = <0 0x10212000 0 0x80>,
			<0 0x10212080 0 0x80>,
			<0 0x10212100 0 0x80>;
		interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>,
			<GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>,
			<GIC_SPI 136 IRQ_TYPE_LEVEL_LOW>;
		nr_channel = <3>;
		clocks = <&infracfg_ao CLK_IFR_CQ_DMA>;
		clock-names = "cqdma";
	};

	mcupm_sram3@10213000 {
		compatible = "mediatek,mcupm_sram3";
		reg = <0 0x10213000 0 0x1000>;
	};

	sramrom@10214000 {
		compatible = "mediatek,sramrom";
		reg = <0 0x10214000 0 0x1000>;
	};

	mcupm_reg@10216000 {
		compatible = "mediatek,mcupm_reg";
		reg = <0 0x10216000 0 0x1000>;
	};

	mcupm_sram0@10217000 {
		compatible = "mediatek,mcupm_sram0";
		reg = <0 0x10217000 0 0x1000>;
	};

	mcupm_sram1@10218000 {
		compatible = "mediatek,mcupm_sram1";
		reg = <0 0x10218000 0 0x1000>;
	};

	emi@10219000 {
		compatible = "mediatek,emi";
		reg = <0 0x10219000 0 0x1000>, /* CEN EMI */
			<0 0x10226000 0 0x1000>, /* MPU */
			<0 0x1022d000 0 0x1000>, /* CH0 EMI */
			<0 0x10235000 0 0x1000>, /* CH1 EMI */
			<0 0x1020e000 0 0x1000>; /* dbg0 */
		interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
	};

	chn_emi@1021a000 {
		compatible = "mediatek,chn_emi";
		reg = <0 0x1021a000 0 0x1000>;
	};

	apcldmain@1021b000 {
		compatible = "mediatek,apcldmain";
		reg = <0 0x1021b000 0 0x100>;
	};

	apcldmain@1021b100 {
		compatible = "mediatek,apcldmain";
		reg = <0 0x1021b100 0 0x100>;
	};

	apcldmaout@1021b400 {
		compatible = "mediatek,apcldmaout";
		reg = <0 0x1021b400 0 0x100>;
	};

	apcldmaout@1021b500 {
		compatible = "mediatek,apcldmaout";
		reg = <0 0x1021b500 0 0x100>;
	};

	apcldmamisc@1021b800 {
		compatible = "mediatek,apcldmamisc";
		reg = <0 0x1021b800 0 0x100>;
		interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
	};

	apcldmamisc@1021b900 {
		compatible = "mediatek,apcldmamisc";
		reg = <0 0x1021b900 0 0x400>;
	};

	mdcldmain@1021c000 {
		compatible = "mediatek,mdcldmain";
		reg = <0 0x1021c000 0 0x400>;
	};

	mdcldmaout@1021c400 {
		compatible = "mediatek,mdcldmaout";
		reg = <0 0x1021c400 0 0x400>;
	};

	mdcldmamisc@1021c000 {
		compatible = "mediatek,mdcldmamisc";
		reg = <0 0x1021c000 0 0x1000>;
	};

	mdcldmamisc@1021c900 {
		compatible = "mediatek,mdcldmamisc";
		reg = <0 0x1021c900 0 0x400>;
	};

	mdcldma:mdcldma@10014000 {
		compatible = "mediatek,mdcldma";
		/*
		 * AP_CLDMA_AO "mediatek,apcldmain_ao"
		 * AP_CLDMA_PDN "mediatek,apcldmain"
		 * AP_CCIF_BASE "mediatek,ap_ccif0"
		 * MD_CCIF_BASE "mediatek,md_ccif0"
		 */
		reg =	<0 0x10014000 0 0x1000>,
			<0 0x1021b000 0 0x1000>,
			<0 0x10209000 0 0x1000>,
			<0 0x1020a000 0 0x1000>;
		/*
		 * IRQ_CLDMA "mediatek,apcldmamisc"
		 * IRQ_CCIF0 "mediatek,ap_ccif0"
		 * IRQ_CCIF1
		 * IRQ_MDWDT "mediatek,md_rgu"
		 */
		interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 75 IRQ_TYPE_EDGE_FALLING>;
		mediatek,md_id = <0>;
		mediatek,cldma_capability = <6>;
		clocks = <&scpsys SCP_SYS_MD1>,
			<&infracfg_ao CLK_IFR_CLDMA_BCLK>,
			<&infracfg_ao CLK_IFR_CCIF_AP>,
			<&infracfg_ao CLK_IFR_CCIF_MD>,
			<&infracfg_ao CLK_IFR_CCIF1_AP>,
			<&infracfg_ao CLK_IFR_CCIF1_MD>,
			<&infracfg_ao CLK_IFR_CCIF2_AP>,
			<&infracfg_ao CLK_IFR_CCIF2_MD>;
		clock-names = "scp-sys-md1-main",
			"infra-cldma-bclk",
			"infra-ccif-ap",
			"infra-ccif-md",
			"infra-ccif1-ap",
			"infra-ccif1-md",
			"infra-ccif2-ap",
			"infra-ccif2-md";
	};

	md_auxadc:md_auxadc {
		compatible = "mediatek,md_auxadc";
		io-channels = <&auxadc 2>;
		io-channel-names = "md-channel";
	};

	bpi_bsi_slv0@1021e000 {
		compatible = "mediatek,bpi_bsi_slv0";
		reg = <0 0x1021e000 0 0x1000>;
	};

	bpi_bsi_slv1@1021f000 {
		compatible = "mediatek,bpi_bsi_slv1";
		reg = <0 0x1021f000 0 0x6000>;
	};

	bpi_bsi_slv2@10225000 {
		compatible = "mediatek,bpi_bsi_slv2";
		reg = <0 0x10225000 0 0x1000>;
	};

	emi_mpu@10226000 {
		compatible = "mediatek,emi_mpu";
		reg = <0 0x10226000 0 0x1000>;
	};

	dvfsp@10227000 {
		compatible = "mediatek,dvfsp";
		reg = <0 0x10227000 0 0x1000>;
	};

	dvfsp: dvfsp@00110800 {
		compatible = "mediatek,mt6768-dvfsp";
		reg = <0 0x00110800 0 0x1400>,
		      <0 0x00110800 0 0x1400>;
		state = <1>;
		change_flag = <0>;
		little-rise-time = <1000>;
		little-down-time = <750>;
		big-rise-time = <1000>;
		big-down-time = <750>;
		L-table = <1700 56 2 1
			   1625 53 2 1
			   1500 48 2 1
			   1450 46 2 1
			   1375 43 2 1
			   1325 41 2 1
			   1275 39 2 1
			   1175 34 2 1
			   1100 41 2 1
			   1050 29 2 1
			    999 27 2 1
			    950 25 2 1
			    900 23 2 1
			    850 21 4 1
			    774 19 4 1
			    500 16 4 1 >;

		B-table = <2000 72 1 1
			   1950 69 1 1
			   1900 65 1 1
			   1850 61 1 1
			   1800 58 1 1
			   1710 54 1 1
			   1621 50 1 1
			   1548 48 2 1
			   1443 43 2 1
			   1354 39 2 1
			   1265 36 2 1
			   1176 32 2 1
			   1087 29 2 1
			    998 25 2 1
			    909 22 2 1
			    850 19 2 1 >;

		CCI-table = <1187 56 2 1
			     1120 52 2 1
			     1049 48 2 1
			     1014 46 2 1
			      961 43 2 1
			      909 40 2 1
			      856 36 2 1
			      821 34 2 1
			      768 31 2 1
			      733 29 4 1
			      698 27 4 1
			      663 25 4 1
			      628 23 4 1
			      593 21 4 1
			      58  19 4 1
			      500 16 4 1 >;

	};

	mt_cpufreq: mt_cpufreq {
		compatible = "mediatek,mt-cpufreq";
	};

	dramc@1022a000 {
		compatible = "mediatek,dramc";
		reg = <0 0x1022a000 0 0x2000>, /* DRAMC AO CHA */
			<0 0x10232000 0 0x2000>, /* DRAMC AO CHB */
			<0 0x1022c000 0 0x1000>, /* DRAMC NAO CHA */
			<0 0x10234000 0 0x1000>, /* DRAMC NAO CHB */
			<0 0x10228000 0 0x2000>, /* DDRPHY AO CHA */
			<0 0x10230000 0 0x2000>, /* DDRPHY AO CHB */
			<0 0x1022e000 0 0x1000>, /* DDRPHY NAO CHA */
			<0 0x10236000 0 0x1000>; /* DDRPHY NAO CHB */
	};
	gce: gce@10238000 {
		compatible = "mediatek,gce", "syscon";
		reg = <0 0x10238000 0 0x4000>;
		#clock-cells = <1>;
		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_LOW>;
		disp_mutex_reg = <0x14016000 0x1000>;
		g3d_config_base = <0x13000000 0 0xffff0000>;
		mmsys_config_base = <0x14000000 1 0xffff0000>;
		disp_dither_base = <0x14010000 2 0xffff0000>;
		mm_na_base = <0x14020000 3 0xffff0000>;
		imgsys_base = <0x15020000 4 0xffff0000>;
		vdec_gcon_base = <0x18800000 5 0xffff0000>;
		venc_gcon_base = <0x18810000 6 0xffff0000>;
		conn_peri_base = <0x18820000 7 0xffff0000>;
		topckgen_base = <0x18830000 8 0xffff0000>;
		kp_base = <0x18840000 9 0xffff0000>;
		scp_sram_base = <0x10000000 10 0xffff0000>;
		infra_na3_base = <0x10010000 11 0xffff0000>;
		infra_na4_base = <0x10020000 12 0xffff0000>;
		scp_base = <0x10030000 13 0xffff0000>;
		mcucfg_base = <0x10040000 14 0xffff0000>;
		gcpu_base = <0x10050000 15 0xffff0000>;
		usb0_base = <0x10200000 16 0xffff0000>;
		usb_sif_base = <0x10280000 17 0xffff0000>;
		audio_base = <0x17000000 18 0xffff0000>;
		vdec_base = <0x17010000 19 0xffff0000>;
		msdc2_base = <0x17020000 20 0xffff0000>;
		vdec1_base = <0x17030000 21 0xffff0000>;
		msdc3_base = <0x18000000 22 0xffff0000>;
		ap_dma_base = <0x18010000 23 0xffff0000>;
		gce_base = <0x18020000 24 0xffff0000>;
		vdec2_base = <0x18040000 25 0xffff0000>;
		vdec3_base = <0x18050000 26 0xffff0000>;
		camsys_base = <0x18080000 27 0xffff0000>;
		camsys1_base = <0x180a0000 28 0xffff0000>;
		camsys2_base = <0x180b0000 29 0xffff0000>;
		pwm_sw_base = <0x1100e000 99 0xffff0000>;
		mdp_rdma0_sof = <0>;
		mdp_ccorr0_sof = <1>;
		mdp_rsz0_sof = <2>;
		mdp_rsz1_sof = <3>;
		mdp_wdma_sof = <4>;
		mdp_wrot0_sof = <5>;
		mdp_tdshp0_sof = <6>;
		disp_ovl0_sof = <7>;
		disp_2l_ovl0_sof = <8>;
		disp_rdma0_sof = <9>;
		disp_wdma0_sof = <10>;
		disp_color0_sof = <11>;
		disp_ccorr0_sof = <12>;
		disp_aal0_sof = <13>;
		disp_gamma0_sof = <14>;
		disp_dither0_sof = <15>;
		disp_dsi0_sof = <16>;
		disp_rsz0_sof = <17>;
		img_dl_relay_sof = <18>;
		disp_pwm0_sof = <19>;
		mdp_rdma0_frame_done = <20>;
		mdp_ccorr0_frame_done = <21>;
		mdp_rsz0_frame_done = <22>;
		mdp_rsz1_frame_done = <23>;
		mdp_wrot0_write_frame_done = <24>;
		mdp_wdma_frame_done = <25>;
		mdp_tdshp0_frame_done = <26>;
		disp_ovl0_frame_done = <27>;
		disp_2l_ovl0_frame_done = <28>;
		disp_rsz0_frame_done = <29>;
		disp_rdma0_frame_done = <30>;
		disp_wdma0_frame_done = <31>;
		disp_color0_frame_done = <32>;
		disp_ccorr0_frame_done = <33>;
		disp_aal0_frame_done = <34>;
		disp_gamma0_frame_done = <35>;
		disp_dither0_frame_done = <36>;
		disp_dsi0_frame_done = <37>;
		stream_done_0 = <130>;
		stream_done_1 = <131>;
		stream_done_2 = <132>;
		stream_done_3 = <133>;
		stream_done_4 = <134>;
		stream_done_5 = <135>;
		stream_done_6 = <136>;
		stream_done_7 = <137>;
		stream_done_8 = <138>;
		stream_done_9 = <139>;
		buf_underrun_event_0 = <140>;
		dsi0_te_event = <141>;
		dsi0_irq_event = <142>;
		dsi0_done_event = <143>;
		disp_wdma0_rst_done = <147>;
		mdp_wdma_rst_done = <148>;
		mdp_wrot0_rst_done = <149>;
		mdp_rdma0_rst_done = <151>;
		disp_ovl0_frame_rst_done_pusle = <152>;
		dip_cq_thread0_frame_done = <257>;
		dip_cq_thread1_frame_done = <258>;
		dip_cq_thread2_frame_done = <259>;
		dip_cq_thread3_frame_done = <260>;
		dip_cq_thread4_frame_done = <261>;
		dip_cq_thread5_frame_done = <262>;
		dip_cq_thread6_frame_done = <263>;
		dip_cq_thread7_frame_done = <264>;
		dip_cq_thread8_frame_done = <265>;
		dip_cq_thread9_frame_done = <266>;
		dip_cq_thread10_frame_done = <267>;
		dip_cq_thread11_frame_done = <268>;
		dip_cq_thread12_frame_done = <269>;
		dip_cq_thread13_frame_done = <270>;
		dip_cq_thread14_frame_done = <271>;
		dip_cq_thread15_frame_done = <272>;
		dip_cq_thread16_frame_done = <273>;
		dip_cq_thread17_frame_done = <274>;
		dip_cq_thread18_frame_done = <275>;
		dve_frame_done = <276>;
		wmf_frame_done = <277>;
		rsc_frame_done = <278>;
		venc_frame_done = <289>;
		venc_pause_done = <290>;
		jpgenc_done = <291>;
		venc_mb_done = <292>;
		venc_128byte_cnt_done = <293>;
		isp_frame_done_b = <322>;
		camsv_0_pass1_done = <323>;
		camsv_1_pass1_done = <324>;
		camsv_2_pass1_done = <325>;
		tsf_done = <326>;
		seninf_0_fifo_full = <327>;
		seninf_1_fifo_full = <328>;
		seninf_2_fifo_full = <329>;
		seninf_3_fifo_full = <330>;
		seninf_4_fifo_full = <331>;
		seninf_5_fifo_full = <332>;
		seninf_6_fifo_full = <333>;
		seninf_7_fifo_full = <334>;
		dsi0_te_from_infra = <898>;
		mmsys_config = <&mmsys_config>;
		mdp_rdma0 = <&mdp_rdma0>;
		mdp_rsz0 = <&mdp_rsz0>;
		mdp_rsz1 = <&mdp_rsz1>;
		mdp_wdma0 = <&mdp_wdma0>;
		mdp_wrot0 = <&mdp_wrot0>;
		mdp_tdshp0 = <&mdp_tdshp0>;
		mdp_color0 = <&disp_color0>;
		mdp_ccorr0 = <&mdp_ccorr>;
		mm_mutex = <&disp_mutex0>;
		sram_share_cnt = <1>;
		sram_share_engine = <13>;
		sram_share_event = <710>;
		mediatek,mailbox-gce = <&gce_mbox>;
		secure_thread = <6 8>;
		mboxes = <&gce_mbox 0 0 CMDQ_THR_PRIO_4>,
			<&gce_mbox 2 0 CMDQ_THR_PRIO_5>,
			<&gce_mbox 3 0 CMDQ_THR_PRIO_4>,
			<&gce_mbox 4 0 CMDQ_THR_PRIO_4>,
			<&gce_mbox 6 0 CMDQ_THR_PRIO_3>,
			<&gce_mbox 7 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_2>,
#if defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT) || \
defined(CONFIG_MTK_CAM_SECURITY_SUPPORT)
			<&gce_mbox_svp 8 0 CMDQ_THR_PRIO_4>,
			<&gce_mbox_svp 9 0 CMDQ_THR_PRIO_4>,
			<&gce_mbox_svp 10 0 CMDQ_THR_PRIO_1>,
#else
			<&gce_mbox 8 0 CMDQ_THR_PRIO_1>,
			<&gce_mbox 9 0 CMDQ_THR_PRIO_1>,
			<&gce_mbox 10 0 CMDQ_THR_PRIO_1>,
#endif
			<&gce_mbox 11 0 CMDQ_THR_PRIO_1>,
			<&gce_mbox 12 0 CMDQ_THR_PRIO_1>,
			<&gce_mbox 13 0 CMDQ_THR_PRIO_1>,
			<&gce_mbox 14 0 CMDQ_THR_PRIO_1>,
			<&gce_mbox 15 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_1>;
		clocks = <&infracfg_ao CLK_IFR_GCE>,
			<&infracfg_ao CLK_IFR_GCE_26M>,
			<&scpsys SCP_SYS_DIS>;
		clock-names = "GCE", "GCE_TIMER", "MMSYS_MTCMOS";
	};

	gce_mbox: gce_mbox@10238000 {
		compatible = "mediatek,mt6768-gce";
		reg = <0 0x10238000 0 0x4000>;
		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_LOW>;
		default_tokens = /bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_0>,
			/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_1>,
			/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_2>,
			/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_3>,
			/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_4>,
			/bits/ 16 <CMDQ_SYNC_RESOURCE_WROT0>,
			/bits/ 16 <CMDQ_SYNC_RESOURCE_WROT1>;
		clocks = <&infracfg_ao CLK_IFR_GCE>,
			<&infracfg_ao CLK_IFR_GCE_26M>;
		clock-names = "gce", "gce-timer";
		#mbox-cells = <3>;
		#gce-event-cells = <1>;
		#gce-subsys-cells = <2>;
	};

#if defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT) || \
	defined(CONFIG_MTK_CAM_SECURITY_SUPPORT)
	gce_mbox_svp: gce_mbox_svp@10238000 {
		compatible = "mediatek,mailbox-gce-svp";
		reg = <0 0x10238000 0 0x4000>;
		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_LOW>,
			<GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>;
		#mbox-cells = <3>;
		clocks = <&infracfg_ao CLK_IFR_GCE>,
			<&infracfg_ao CLK_IFR_GCE_26M>;
		clock-names = "gce", "gce-timer";
	};
#endif

	ap_ccif2@1023c000 {
		compatible = "mediatek,ap_ccif2";
		reg = <0 0x1023c000 0 0x1000>;
		interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_LOW>;
	};

	md_ccif2@1023d000 {
		compatible = "mediatek,md_ccif2";
		reg = <0 0x1023d000 0 0x1000>;
	};

	ap_ccif3@1023e000 {
		compatible = "mediatek,ap_ccif3";
		reg = <0 0x1023e000 0 0x1000>;
		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_LOW>;
	};

	goodix_fp: fingerprint {
		compatible = "mediatek,fpc1022_irq","mediatek,goodix-fp";
		status = "okay";
	};

	accdet: accdet {
		compatible = "mediatek,pmic-accdet";
	};

	swtp: swtp {
		compatible = "mediatek, swtp-eint";
		ant_sw_gpios = <&pio 72 0>;
	};

	mt6358_gauge {
		compatible = "mediatek,mt6358_gauge";
		gauge_name = "gauge";
		alias_name = "MT6358";
	};

	gauge_timer {
		compatible = "mediatek,gauge_timer_service";
	};
	simtray {
		compatible = "xiaomi,simtray-status";
		status-gpio = <&pio 46 0>;
	};
#if (CONFIG_MTK_GAUGE_VERSION == 30)
	#include "mediatek/bat_setting/mt6768_battery_prop.dtsi"
#endif

	md_ccif3@1023f000 {
		compatible = "mediatek,md_ccif3";
		reg = <0 0x1023f000 0 0x1000>;
	};

	sspm@10440000 {
		compatible = "mediatek,sspm";
		reg = <0 0x10440000 0 0x10000>,
			<0 0x10450000 0 0x100>,
			<0 0x10451000 0 0x8>,
			<0 0x10460000 0 0x100>,
			<0 0x10461000 0 0x8>,
			<0 0x10470000 0 0x100>,
			<0 0x10471000 0 0x8>,
			<0 0x10480000 0 0x100>,
			<0 0x10481000 0 0x8>,
			<0 0x10490000 0 0x100>,
			<0 0x10491000 0 0x8>;

		reg-names = "cfgreg",
			"mbox0_base",
			"mbox0_ctrl",
			"mbox1_base",
			"mbox1_ctrl",
			"mbox2_base",
			"mbox2_ctrl",
			"mbox3_base",
			"mbox3_ctrl",
			"mbox4_base",
			"mbox4_ctrl";

		interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "ipc",
			"mbox0",
			"mbox1",
			"mbox2",
			"mbox3",
			"mbox4";
	};

	gic500@0c000000 {
		compatible = "mediatek,gic500";
		reg = <0 0x0c000000 0 0x400000>;
	};

	gic_cpu@0c400000 {
		compatible = "mediatek,gic_cpu";
		reg = <0 0x0c400000 0 0x40000>;
	};

	lastbus@10001000 {
		compatible = "mediatek,lastbus-v1";
		reg = <0 0x10001000 0 0x1000>,
			<0 0x10003000 0 0x1000>;
	};

	dfd@10200b00 {
		compatible = "mediatek,dfd";
		reg = <0 0x10200b00 0 0x10000>;

		mediatek,enabled = <1>;
		mediatek,chain_length = <0xa7f8>;
		mediatek,rg_dfd_timeout = <0xa0>;
	};

	dfd_cache: dfd_cache {
		compatible = "mediatek,dfd_cache";
		mediatek,enabled = <0>;
		mediatek,rg_dfd_timeout = <0x3e80>;
	};

	dbg_cti@0d020000 {
		compatible = "mediatek,dbg_cti";
		reg = <0 0x0d020000 0 0x10000>;
	};

	dbg_etr@0d030000 {
		compatible = "mediatek,dbg_etr";
		reg = <0 0x0d030000 0 0x10000>;
	};

	dbg_funnel@0d040000 {
		compatible = "mediatek,dbg_funnel";
		reg = <0 0x0d040000 0 0x10000>;
	};

	dbg_dem@0d0a0000 {
		compatible = "mediatek,dbg_dem";
		reg = <0 0x0d0a0000 0 0x10000>;
		interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW>;
	};

	dbg_mdsys1@0d0c0000 {
		compatible = "mediatek,dbg_mdsys1";
		reg = <0 0x0d0c0000 0 0x40000>;
	};

	dbg_apmcu_mp0@0d400000 {
		compatible = "mediatek,dbg_apmcu_mp0";
		reg = <0 0x0d400000 0 0x1000>;
	};

	dbg_apmcu_mp0@0d410000 {
		compatible = "mediatek,dbg_apmcu_mp0";
		reg = <0 0x0d410000 0 0x1000>;
	};

	dbg_apmcu_mp0@0d420000 {
		compatible = "mediatek,dbg_apmcu_mp0";
		reg = <0 0x0d420000 0 0x1000>;
	};

	dbg_apmcu_mp0@0d430000 {
		compatible = "mediatek,dbg_apmcu_mp0";
		reg = <0 0x0d430000 0 0x1000>;
	};

	dbg_apmcu_mp0@0d440000 {
		compatible = "mediatek,dbg_apmcu_mp0";
		reg = <0 0x0d440000 0 0x1000>;
	};

	dbg_apmcu_mp0@0d510000 {
		compatible = "mediatek,dbg_apmcu_mp0";
		reg = <0 0x0d510000 0 0x1000>;
	};

	dbg_apmcu_mp0@0d520000 {
		compatible = "mediatek,dbg_apmcu_mp0";
		reg = <0 0x0d520000 0 0x1000>;
	};

	dbg_apmcu_mp0@0d530000 {
		compatible = "mediatek,dbg_apmcu_mp0";
		reg = <0 0x0d530000 0 0x1000>;
	};

	dbg_apmcu_mp0@0d540000 {
		compatible = "mediatek,dbg_apmcu_mp0";
		reg = <0 0x0d540000 0 0x1000>;
	};

	dbg_apmcu_mp0@0d610000 {
		compatible = "mediatek,dbg_apmcu_mp0";
		reg = <0 0x0d610000 0 0x1000>;
	};

	dbg_apmcu_mp0@0d620000 {
		compatible = "mediatek,dbg_apmcu_mp0";
		reg = <0 0x0d620000 0 0x1000>;
	};

	dbg_apmcu_mp0@0d630000 {
		compatible = "mediatek,dbg_apmcu_mp0";
		reg = <0 0x0d630000 0 0x1000>;
	};

	dbg_apmcu_mp0@0d640000 {
		compatible = "mediatek,dbg_apmcu_mp0";
		reg = <0 0x0d640000 0 0x1000>;
	};

	dbg_apmcu_mp0@0d710000 {
		compatible = "mediatek,dbg_apmcu_mp0";
		reg = <0 0x0d710000 0 0x1000>;
	};

	dbg_apmcu_mp0@0d720000 {
		compatible = "mediatek,dbg_apmcu_mp0";
		reg = <0 0x0d720000 0 0x1000>;
	};

	dbg_apmcu_mp0@0d730000 {
		compatible = "mediatek,dbg_apmcu_mp0";
		reg = <0 0x0d730000 0 0x1000>;
	};

	dbg_apmcu_mp0@0d740000 {
		compatible = "mediatek,dbg_apmcu_mp0";
		reg = <0 0x0d740000 0 0x1000>;
	};

	dbg_apmcu_mp1@0d800000 {
		compatible = "mediatek,dbg_apmcu_mp1";
		reg = <0 0x0d800000 0 0x1000>;
	};

	dbg_apmcu_mp1@0d810000 {
		compatible = "mediatek,dbg_apmcu_mp1";
		reg = <0 0x0d810000 0 0x1000>;
	};

	dbg_apmcu_mp1@0d820000 {
		compatible = "mediatek,dbg_apmcu_mp1";
		reg = <0 0x0d820000 0 0x1000>;
	};

	dbg_apmcu_mp1@0d830000 {
		compatible = "mediatek,dbg_apmcu_mp1";
		reg = <0 0x0d830000 0 0x1000>;
	};

	dbg_apmcu_mp1@0d840000 {
		compatible = "mediatek,dbg_apmcu_mp1";
		reg = <0 0x0d840000 0 0x1000>;
	};

	dbg_apmcu_mp1@0d910000 {
		compatible = "mediatek,dbg_apmcu_mp1";
		reg = <0 0x0d910000 0 0x1000>;
	};

	dbg_apmcu_mp1@0d920000 {
		compatible = "mediatek,dbg_apmcu_mp1";
		reg = <0 0x0d920000 0 0x1000>;
	};

	dbg_apmcu_mp1@0d930000 {
		compatible = "mediatek,dbg_apmcu_mp1";
		reg = <0 0x0d930000 0 0x1000>;
	};

	dbg_apmcu_mp1@0d940000 {
		compatible = "mediatek,dbg_apmcu_mp1";
		reg = <0 0x0d940000 0 0x1000>;
	};

	dbg_apmcu_mp1@0da10000 {
		compatible = "mediatek,dbg_apmcu_mp1";
		reg = <0 0x0da10000 0 0x1000>;
	};

	dbg_apmcu_mp1@0da20000 {
		compatible = "mediatek,dbg_apmcu_mp1";
		reg = <0 0x0da20000 0 0x1000>;
	};

	dbg_apmcu_mp1@0da30000 {
		compatible = "mediatek,dbg_apmcu_mp1";
		reg = <0 0x0da30000 0 0x1000>;
	};

	dbg_apmcu_mp1@0da40000 {
		compatible = "mediatek,dbg_apmcu_mp1";
		reg = <0 0x0da40000 0 0x1000>;
	};

	dbg_apmcu_mp1@0db10000 {
		compatible = "mediatek,dbg_apmcu_mp1";
		reg = <0 0x0db10000 0 0x1000>;
	};

	dbg_apmcu_mp1@0db20000 {
		compatible = "mediatek,dbg_apmcu_mp1";
		reg = <0 0x0db20000 0 0x1000>;
	};

	dbg_apmcu_mp1@0db30000 {
		compatible = "mediatek,dbg_apmcu_mp1";
		reg = <0 0x0db30000 0 0x1000>;
	};

	dbg_apmcu_mp1@0db40000 {
		compatible = "mediatek,dbg_apmcu_mp1";
		reg = <0 0x0db40000 0 0x1000>;
	};

	infra_dbgsystop_cpu0@0e000000 {
		compatible = "mediatek,infra_dbgsystop_cpu0";
		reg = <0 0x0e000000 0 0x100000>;
	};

	infra_dbgsystop_cpu1@0e100000 {
		compatible = "mediatek,infra_dbgsystop_cpu1";
		reg = <0 0x0e100000 0 0x100000>;
	};

	infra_dbgsystop_cpu2@0e200000 {
		compatible = "mediatek,infra_dbgsystop_cpu2";
		reg = <0 0x0e200000 0 0x100000>;
	};

	infra_dbgsystop_cpu3@0e300000 {
		compatible = "mediatek,infra_dbgsystop_cpu3";
		reg = <0 0x0e300000 0 0x100000>;
	};

	infra_dbgsystop_cpu4@0e400000 {
		compatible = "mediatek,infra_dbgsystop_cpu4";
		reg = <0 0x0e400000 0 0x100000>;
	};

	infra_dbgsystop_cpu5@0e500000 {
		compatible = "mediatek,infra_dbgsystop_cpu5";
		reg = <0 0x0e500000 0 0x100000>;
	};

	infra_dbgsystop_cpu6@0e600000 {
		compatible = "mediatek,infra_dbgsystop_cpu6";
		reg = <0 0x0e600000 0 0x100000>;
	};

	infra_dbgsystop_cpu7@0e700000 {
		compatible = "mediatek,infra_dbgsystop_cpu7";
		reg = <0 0x0e700000 0 0x100000>;
	};

	ap_dma@11000000 {
		compatible = "mediatek,ap_dma";
		reg = <0 0x11000000 0 0x1000>;
		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_LOW>;
	};

	auxadc: auxadc@11001000 {
		compatible = "mediatek,mt6768-auxadc";
		reg = <0 0x11001000 0 0x1000>;
		interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_FALLING>;
		clocks = <&infracfg_ao CLK_IFR_AUXADC>;
		clock-names = "main";
		#io-channel-cells = <1>;
		/* Auxadc efuse calibration */
		/* 1. Auxadc cali on/off bit shift */
		mediatek,cali-en-bit = <20>;
		/* 2. Auxadc cali ge bits shift */
		mediatek,cali-ge-bit = <10>;
		/* 3. Auxadc cali oe bits shift */
		mediatek,cali-oe-bit = <0>;
		/* 4. Auxadc cali efuse index */
		mediatek,cali-efuse-index = <106>;
	};

	apdma: dma-controller@11000980 {
		compatible = "mediatek,mt6577-uart-dma";
		reg = <0 0x11000980 0 0x80>,
		      <0 0x11000A00 0 0x80>,
		      <0 0x11000A80 0 0x80>,
		      <0 0x11000B00 0 0x80>;
		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infracfg_ao CLK_IFR_AP_DMA>;
		clock-names = "apdma";
		#dma-cells = <1>;
		dma-bits = <34>;
	};

	apuart0: serial@11002000 {
		compatible = "mediatek,mt6577-uart";
		reg = <0 0x11002000 0 0x1000>;
		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&clk26m>, <&infracfg_ao CLK_IFR_UART0>;
		clock-names = "baud", "bus";
		dmas = <&apdma 0
				&apdma 1>;
		dma-names = "tx", "rx";
	};

	apuart1: serial@11003000 {
		compatible = "mediatek,mt6577-uart";
		reg = <0 0x11003000 0 0x1000>;
		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
		clocks =  <&clk26m>, <&infracfg_ao CLK_IFR_UART1>;
		clock-names = "baud", "bus";
		dmas = <&apdma 2
				&apdma 3>;
		dma-names = "tx", "rx";
	};

	i2c_common: i2c_common {
		compatible = "mediatek,i2c_common";
		dma_support = /bits/ 8 <3>;
		idvfs = /bits/ 8 <1>;
		set_dt_div = /bits/ 8 <1>;
		check_max_freq = /bits/ 8 <1>;
		ver = /bits/ 8 <2>;
		set_ltiming = /bits/ 8 <1>;
		ext_time_config = /bits/ 16 <0x1801>;
		cnt_constraint = /bits/ 8 <1>;
		control_irq_sel = /bits/ 8 <1>;
	};

	pwm@11006000 {
		compatible = "mediatek,pwm";
		reg = <0 0x11006000 0 0x1000>;
		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infracfg_ao CLK_IFR_PWM1>,
			<&infracfg_ao CLK_IFR_PWM2>,
			<&infracfg_ao CLK_IFR_PWM3>,
			<&infracfg_ao CLK_IFR_PWM4>,
			<&infracfg_ao CLK_IFR_PWM5>,
			<&infracfg_ao CLK_IFR_RG_PWM_FBCLK6>,
			<&infracfg_ao CLK_IFR_PWM_HCLK>,
			<&infracfg_ao CLK_IFR_PWM>;

		clock-names = "PWM1-main",
			"PWM2-main",
			"PWM3-main",
			"PWM4-main",
			"PWM5-main",
			"PWM6-main",
			"PWM-HCLK-main",
			"PWM-main";
	};

	i2c0: i2c0@11007000 {
		compatible = "mediatek,i2c";
		id = <0>;
		reg = <0 0x11007000 0 0x1000>,
			<0 0x11000080 0 0x80>;
		interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infracfg_ao CLK_IFR_I2C_AP>,
			<&infracfg_ao CLK_IFR_AP_DMA>;
		clock-names = "main", "dma";
		clock-div = <5>;
		scl-gpio-id = <83>;
		sda-gpio-id = <82>;
		gpio_start = <0x10002a00>;
		mem_len = <0x200>;
		eh_cfg = <0x30>;
		pu_cfg = <0x70>;
		rsel_cfg = <0x90>;
		aed = <0x1a>;
	};

	i2c1: i2c1@11008000 {
		compatible = "mediatek,i2c";
		id = <1>;
		reg = <0 0x11008000 0 0x1000>,
			<0 0x11000100 0 0x80>;
		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infracfg_ao CLK_IFR_I2C_AP>,
			<&infracfg_ao CLK_IFR_AP_DMA>;
		clock-names = "main", "dma";
		clock-div = <5>;
		scl-gpio-id = <84>;
		sda-gpio-id = <81>;
		gpio_start = <0x10002a00>;
		mem_len = <0x200>;
		eh_cfg = <0x30>;
		pu_cfg = <0x70>;
		rsel_cfg = <0x90>;
		aed = <0x1a>;
	};

	i2c2: i2c2@11009000 {
		compatible = "mediatek,i2c";
		id = <2>;
		reg = <0 0x11009000 0 0x1000>,
			<0 0x11000180 0 0x180>;
		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infracfg_ao CLK_IFR_I2C_AP>,
			<&infracfg_ao CLK_IFR_AP_DMA>;
		clock-names = "main", "dma";
		clock-div = <5>;
		scl-gpio-id = <103>;
		sda-gpio-id = <104>;
		gpio_start = <0x10002800>;
		mem_len = <0x200>;
		eh_cfg = <0x40>;
		pu_cfg = <0xa0>;
		rsel_cfg = <0xf0>;
		aed = <0x1a>;
		ch_offset_default = <0x100>;
		ch_offset_ccu = <0x200>;
	};

	i2c3: i2c3@1100f000 {
		compatible = "mediatek,i2c";
		id = <3>;
		reg = <0 0x1100f000 0 0x1000>,
			<0 0x11000300 0 0x100>;
		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infracfg_ao CLK_IFR_I2C_AP>,
			<&infracfg_ao CLK_IFR_AP_DMA>;
		clock-names = "main", "dma";
		clock-div = <5>;
		scl-gpio-id = <50>;
		sda-gpio-id = <51>;
		gpio_start = <0x10002600>;
		mem_len = <0x200>;
		eh_cfg = <0x30>;
		pu_cfg = <0x60>;
		rsel_cfg = <0x90>;
		aed = <0x1a>;
		ch_offset_default = <0x100>;
		ch_offset_ccu = <0x200>;
	};

	i2c4: i2c4@11011000 {
		compatible = "mediatek,i2c";
		id = <4>;
		reg = <0 0x11011000 0 0x1000>,
			<0 0x11000400 0 0x180>;
		interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infracfg_ao CLK_IFR_I2C_AP>,
			<&infracfg_ao CLK_IFR_AP_DMA>;
		clock-names = "main", "dma";
		clock-div = <5>;
		scl-gpio-id = <105>;
		sda-gpio-id = <106>;
		gpio_start = <0x10002800>;
		mem_len = <0x200>;
		eh_cfg = <0x40>;
		pu_cfg = <0xa0>;
		rsel_cfg = <0xf0>;
		aed = <0x1a>;
		ch_offset_default = <0x100>;
		ch_offset_ccu = <0x200>;
	};

	i2c5: i2c5@11016000 {
		compatible = "mediatek,i2c";
		id = <5>;
		reg = <0 0x11016000 0 0x1000>,
			<0 0x11000580 0 0x80>;
		interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infracfg_ao CLK_IFR_I2C_AP>,
			<&infracfg_ao CLK_IFR_AP_DMA>;
		clock-names = "main", "dma";
		clock-div = <5>;
		scl-gpio-id = <48>;
		sda-gpio-id = <49>;
		gpio_start = <0x10002600>;
		mem_len = <0x200>;
		eh_cfg = <0x30>;
		pu_cfg = <0x60>;
		rsel_cfg = <0x90>;
		aed = <0x1a>;
	};

	i2c6: i2c6@1100d000 {
		compatible = "mediatek,i2c";
		id = <6>;
		reg = <0 0x1100d000 0 0x1000>,
			<0 0x11000600 0 0x80>;
		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infracfg_ao CLK_IFR_I2C_AP>,
			<&infracfg_ao CLK_IFR_AP_DMA>;
		clock-names = "main", "dma";
		clock-div = <5>;
		scl-gpio-id = <89>;
		sda-gpio-id = <90>;
		gpio_start = <0x10002000>;
		mem_len = <0x200>;
		eh_cfg = <0x30>;
		pu_cfg = <0x60>;
		rsel_cfg = <0x90>;
		aed = <0x1a>;
	};

	i2c7: i2c7@11004000 {
		compatible = "mediatek,i2c";
		id = <7>;
		reg = <0 0x11004000 0 0x1000>,
			<0 0x11000680 0 0x180>;
		interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infracfg_ao CLK_IFR_I2C_AP>,
			<&infracfg_ao CLK_IFR_AP_DMA>;
		clock-names = "main", "dma";
		clock-div = <5>;
		scl-gpio-id = <175>;
		sda-gpio-id = <176>;
		gpio_start = <0x10002600>;
		mem_len = <0x200>;
		eh_cfg = <0x30>;
		pu_cfg = <0x60>;
		rsel_cfg = <0x90>;
		aed = <0x1a>;
	};

	i2c8: i2c8@11005000 {
		compatible = "mediatek,i2c";
		id = <8>;
		reg = <0 0x11005000 0 0x1000>,
			<0 0x11000800 0 0x180>;
		interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infracfg_ao CLK_IFR_I2C_AP>,
			<&infracfg_ao CLK_IFR_AP_DMA>;
		clock-names = "main", "dma";
		clock-div = <5>;
		aed = <0x1a>;
	};

	spi0:spi0@1100a000 {
		compatible = "mediatek,mt6765-spi";
		mediatek,pad-select = <0>;
		reg = <0 0x1100a000 0 0x1000>;
		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
			 <&topckgen CLK_TOP_SPI_SEL>,
			 <&infracfg_ao CLK_IFR_SPI0>;
		clock-names = "parent-clk", "sel-clk", "spi-clk";
	};

	eem_fsm: eem_fsm@1100b000 {
		compatible = "mediatek,eem_fsm";
		reg = <0 0x1100b000 0 0x1000>;
		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
		eem-status = <1>;
		eem-initmon-little = <0xf>;
		eem-initmon-big = <0xf>;
		eem-initmon-cci = <0xf>;
		eem-initmon-gpu = <0xf>;
		eem-clamp-little = <0>;
		eem-clamp-big = <0>;
		eem-clamp-cci = <0>;
		eem-clamp-gpu = <0>;
		eem-offset-little = <0xff>;
		eem-offset-big = <0xff>;
		eem-offset-cci = <0xff>;
		eem-offset-gpu = <0xff>;
	};

	therm_ctrl@1100b000 {
		compatible = "mediatek,therm_ctrl";
		reg = <0 0x1100b000 0 0x1000>;
		interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infracfg_ao CLK_IFR_THERM>;
		clock-names = "therm-main";
	};

	tboard_thermistor1: thermal-sensor1 {
		compatible = "mediatek,mtboard-thermistor1";
		io-channels = <&auxadc 0>;
		io-channel-names = "thermistor-ch0";
	};

	tboard_thermistor2: thermal-sensor2 {
		compatible = "mediatek,mtboard-thermistor2";
		io-channels = <&auxadc 1>;
		io-channel-names = "thermistor-ch1";
	};

	drcc: drcc {
		compatible = "mediatek,drcc";
		state = <255>;
		drcc0_Vref = <255>;
		drcc1_Vref = <255>;
		drcc2_Vref = <255>;
		drcc3_Vref = <255>;
		drcc4_Vref = <255>;
		drcc5_Vref = <255>;
		drcc6_Vref = <255>;
		drcc7_Vref = <255>;
		drcc0_Hwgatepct = <255>;
		drcc1_Hwgatepct = <255>;
		drcc2_Hwgatepct = <255>;
		drcc3_Hwgatepct = <255>;
		drcc4_Hwgatepct = <255>;
		drcc5_Hwgatepct = <255>;
		drcc6_Hwgatepct = <255>;
		drcc7_Hwgatepct = <255>;
		drcc0_Code = <255>;
		drcc1_Code = <255>;
		drcc2_Code = <255>;
		drcc3_Code = <255>;
		drcc4_Code = <255>;
		drcc5_Code = <255>;
		drcc6_Code = <255>;
		drcc7_Code = <255>;
	};

	btif@1100c000 {
		compatible = "mediatek,btif";
			/*btif base*/
		reg = <0 0x1100c000 0 0x1000>,
			/*btif tx dma base*/
			<0 0x11000b80 0 0x80>,
			/*btif rx dma base*/
			<0 0x11000c00 0 0x80>;
			/*btif irq, IRQS_Sync ID, btif_irq_b*/
		interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>,
			/*btif tx dma irq*/
			<GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>,
			/*btif rx dma irq*/
			<GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infracfg_ao CLK_IFR_BTIF>,
			/*btif clock*/
			<&infracfg_ao CLK_IFR_AP_DMA>;
			/*ap dma clock*/
		clock-names = "btifc","apdmac";
	};

	consys: consys@18002000 {
		compatible = "mediatek,mt6768-consys";
		#address-cells = <2>;
		#size-cells = <2>;
			/*CONN_MCU_CONFIG_BASE */
		reg = <0 0x18002000 0 0x1000>,
			/*TOP_RGU_BASE */
		    <0 0x10007000 0 0x0100>,
			/*INFRACFG_AO_BASE */
		    <0 0x10001000 0 0x1000>,
			/*SPM_BASE */
		    <0 0x10006000 0 0x1000>,
			/*CONN_HIF_ON_BASE */
		    <0 0x18007000 0 0x1000>,
			/*CONN_TOP_MISC_OFF_BASE */
		    <0 0x180b1000 0 0x1000>,
			/*CONN_MCU_CFG_ON_BASE */
		    <0 0x180a3000 0 0x1000>,
			/*CONN_MCU_CIRQ_BASE */
		    <0 0x180a5000 0 0x800>,
			/*CONN_TOP_MISC_ON_BASE */
		    <0 0x180c1000 0 0x1000>,
			/*CONN_HIF_PDMA_BASE */
		    <0 0x18004000 0 0x1000>;
			/*BGF_EINT */
		interrupts = <GIC_SPI 284 IRQ_TYPE_LEVEL_LOW>,
			/*WDT_EINT */
			   <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>,
			/*conn2ap_sw_irq*/
			   <GIC_SPI 287 IRQ_TYPE_EDGE_RISING>;
		clocks = <&scpsys SCP_SYS_CONN>;
		clock-names = "conn";
		wifi_ant_swap_gpio = <&pio 108 0x0>;
	};

	disp_pwm@1100e000 {
		compatible = "mediatek,disp_pwm";
		reg = <0 0x1100e000 0 0x1000>;
	};

	spi1:spi1@11010000 {
		compatible = "mediatek,mt6765-spi";
		mediatek,pad-select = <0>;
		reg = <0 0x11010000 0 0x1000>;
		interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
			 <&topckgen CLK_TOP_SPI_SEL>,
			 <&infracfg_ao CLK_IFR_SPI1>;
		clock-names = "parent-clk", "sel-clk", "spi-clk";
	};

	spi2:spi2@11012000 {
		compatible = "mediatek,mt6765-spi";
		mediatek,pad-select = <0>;
		reg = <0 0x11012000 0 0x1000>;
		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
			 <&topckgen CLK_TOP_SPI_SEL>,
			 <&infracfg_ao CLK_IFR_SPI2>;
		clock-names = "parent-clk", "sel-clk", "spi-clk";
	};

	spi3:spi3@11013000 {
		compatible = "mediatek,mt6765-spi";
		mediatek,pad-select = <0>;
		reg = <0 0x11013000 0 0x1000>;
		interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
			 <&topckgen CLK_TOP_SPI_SEL>,
			 <&infracfg_ao CLK_IFR_SPI3>;
		clock-names = "parent-clk", "sel-clk", "spi-clk";
	};

	spi4:spi4@11014000 {
		compatible = "mediatek,mt6765-spi";
		mediatek,pad-select = <0>;
		reg = <0 0x11014000 0 0x1000>;
		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
			 <&topckgen CLK_TOP_SPI_SEL>,
			 <&infracfg_ao CLK_IFR_SPI4>;
		clock-names = "parent-clk", "sel-clk", "spi-clk";
	};

	spi5:spi5@11015000 {
		compatible = "mediatek,mt6765-spi";
		mediatek,pad-select = <0>;
		reg = <0 0x11015000 0 0x1000>;
		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
			 <&topckgen CLK_TOP_SPI_SEL>,
			 <&infracfg_ao CLK_IFR_SPI5>;
		clock-names = "parent-clk", "sel-clk", "spi-clk";
	};

	imp_iic@11017000 {
		compatible = "mediatek,imp_iic";
		reg = <0 0x11017000 0 0x1000>;
	};

	nfi@11018000 {
		compatible = "mediatek,nfi";
		reg = <0 0x11018000 0 0x1000>;
	};

	nfiecc@11019000 {
		compatible = "mediatek,nfiecc";
		reg = <0 0x11019000 0 0x1000>;
	};

	usb0@11200000 {
		compatible = "mediatek,mt6768-usb20";
		reg = <0 0x11200000 0 0x10000>,
			<0 0x11CC0000 0 0x10000>;
		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
		mode = <2>;
		multipoint = <1>;
		num_eps = <16>;
		clocks = <&infracfg_ao CLK_IFR_ICUSB>,
			<&topckgen CLK_TOP_USB_TOP_SEL>,
			<&topckgen CLK_TOP_UNIVPLL3_D4>;
		clock-names = "usb0",
			"usb0_clk_top_sel",
			"usb0_clk_univpll3_d4";
	};

	msdc0: msdc@11230000 {
		compatible = "mediatek,msdc";
		reg = <0 0x11230000 0 0x10000>;
		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_LOW>;
	};

	msdc1: msdc@11240000 {
		compatible = "mediatek,msdc";
		reg = <0 0x11240000 0 0x10000>;
		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_LOW>;
	};

	msdc0_top@11cd0000 {
		compatible = "mediatek,msdc0_top";
		reg = <0 0x11cd0000 0 0x1000>;
	};

	msdc1_top@11c90000 {
		compatible = "mediatek,msdc1_top";
		reg = <0 0x11c90000 0 0x1000>;
	};

	usb1p_sif@11210000 {
		compatible = "mediatek,usb1p_sif";
		reg = <0 0x11210000 0 0x10000>;
	};

	audio: audio@11220000 {
		compatible = "mediatek,audio", "syscon";
		reg = <0 0x11220000 0 0x1000>;
		#clock-cells = <1>;
	};

	afe: mt6768-afe-pcm@11220000 {
		compatible = "mediatek,mt6768-sound";
		reg = <0 0x11220000 0 0x1000>;
		interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
		topckgen = <&topckgen>;
		apmixed = <&apmixed>;

		clocks = <&audio CLK_AUDIO_AFE>,
			<&audio CLK_AUDIO_DAC>,
			<&audio CLK_AUDIO_DAC_PREDIS>,
			<&audio CLK_AUDIO_ADC>,
			<&audio CLK_AUDIO_22M>,
			<&audio CLK_AUDIO_24M>,
			<&audio CLK_AUDIO_APLL_TUNER>,
			<&audio CLK_AUDIO_TML>,
			<&infracfg_ao CLK_IFR_AUDIO>,
			<&infracfg_ao CLK_IFR_AUDIO_26M_BCLK>,
			<&topckgen CLK_TOP_AUDIO_SEL>,
			<&topckgen CLK_TOP_AUD_INTBUS_SEL>,
			<&topckgen CLK_TOP_SYSPLL1_D4>,
			<&topckgen CLK_TOP_AUD_1_SEL>,
			<&topckgen CLK_TOP_APLL1>,
			<&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
			<&topckgen CLK_TOP_APLL1_D8>,
			<&topckgen CLK_TOP_I2S0_M_SEL>,
			<&topckgen CLK_TOP_I2S1_M_SEL>,
			<&topckgen CLK_TOP_I2S2_M_SEL>,
			<&topckgen CLK_TOP_I2S3_M_SEL>,
			<&topckgen CLK_TOP_APLL12_DIV0>,
			<&topckgen CLK_TOP_APLL12_DIV1>,
			<&topckgen CLK_TOP_APLL12_DIV2>,
			<&topckgen CLK_TOP_APLL12_DIV3>,
			<&apmixed CLK_APMIXED_APLL1>,
			<&clk26m>;
		clock-names = "aud_afe_clk",
			"aud_dac_clk",
			"aud_dac_predis_clk",
			"aud_adc_clk",
			"aud_apll22m_clk",
			"aud_apll24m_clk",
			"aud_apll1_tuner_clk",
			"aud_tml_clk",
			"aud_infra_axi_clk",
			"aud_infra_26m_clk",
			"top_mux_audio",
			"top_mux_audio_int",
			"top_sys_pll1_d4",
			"top_mux_aud_1",
			"top_apll1_ck",
			"top_mux_aud_eng1",
			"top_apll1_d8",
			"top_i2s0_m_sel",
			"top_i2s1_m_sel",
			"top_i2s2_m_sel",
			"top_i2s3_m_sel",
			"top_apll12_div0",
			"top_apll12_div1",
			"top_apll12_div2",
			"top_apll12_div3",
			"apmixed_apll1",
			"top_clk26m_clk";
		pinctrl-names = "aud_clk_mosi_off",
			"aud_clk_mosi_on",
			"aud_clk_miso_off",
			"aud_clk_miso_on",
			"aud_dat_mosi_off",
			"aud_dat_mosi_on",
			"aud_dat_miso_off",
			"aud_dat_miso_on",
			"aud_gpio_i2s0_off",
			"aud_gpio_i2s0_on",
			"aud_gpio_i2s1_off",
			"aud_gpio_i2s1_on",
			"aud_gpio_i2s2_off",
			"aud_gpio_i2s2_on",
			"aud_gpio_i2s3_off",
			"aud_gpio_i2s3_on",
			"vow_dat_miso_off",
			"vow_dat_miso_on",
			"vow_clk_miso_off",
			"vow_clk_miso_on";
		pinctrl-0 = <&aud_clk_mosi_off>;
		pinctrl-1 = <&aud_clk_mosi_on>;
		pinctrl-2 = <&aud_clk_miso_off>;
		pinctrl-3 = <&aud_clk_miso_on>;
		pinctrl-4 = <&aud_dat_mosi_off>;
		pinctrl-5 = <&aud_dat_mosi_on>;
		pinctrl-6 = <&aud_dat_miso_off>;
		pinctrl-7 = <&aud_dat_miso_on>;
		pinctrl-8 = <&aud_gpio_i2s0_off>;
		pinctrl-9 = <&aud_gpio_i2s0_on>;
		pinctrl-10 = <&aud_gpio_i2s1_off>;
		pinctrl-11 = <&aud_gpio_i2s1_on>;
		pinctrl-12 = <&aud_gpio_i2s2_off>;
		pinctrl-13 = <&aud_gpio_i2s2_on>;
		pinctrl-14 = <&aud_gpio_i2s3_off>;
		pinctrl-15 = <&aud_gpio_i2s3_on>;
		pinctrl-16 = <&vow_dat_miso_off>;
		pinctrl-17 = <&vow_dat_miso_on>;
		pinctrl-18 = <&vow_clk_miso_off>;
		pinctrl-19 = <&vow_clk_miso_on>;
	};

	mt6358_snd: mt6358_snd {
		compatible = "mediatek,mt6358-sound";
		mediatek,pwrap-regmap = <&pwrap>;
	};

	sound: sound {
		compatible = "mediatek,mt6768-mt6358-sound";
		mediatek,audio-codec = <&mt6358_snd>;
		mediatek,platform = <&afe>;
		mtk_spk_i2s_out = <3>;
		mtk_spk_i2s_in = <0>;
		/* mtk_spk_i2s_mck = <3>; */
		mediatek,speaker-codec {
			sound-dai = <&speaker_amp>;
		};
	};

	snd_scp_spk: snd_scp_spk {
		compatible = "mediatek,snd_scp_spk";
	};

	audio_sram@11221000 {
		compatible = "mediatek,audio_sram";
		reg = <0 0x11221000 0 0x9000>;
		prefer_mode = <1>;
		mode_size = <0x6c00 0x9000>;
		block_size = <0x1000>;
	};

	mtk-btcvsd-snd@18050000 {
		compatible = "mediatek,mtk-btcvsd-snd";
		reg=<0 0x18050000 0 0x1000>, /*PKV_PHYSICAL_BASE*/
		    <0 0x18080000 0 0x10000>; /*SRAM_BANK2*/
		interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_LOW>;
		mediatek,infracfg = <&infracfg_ao>;
		/*INFRA MISC, conn_bt_cvsd_mask*/
		/*cvsd_mcu_read, write, packet_indicator*/
		mediatek,offset =<0xf00 0x800 0x140 0x144 0x148>;
		disable_write_silence = <0>;
	};

	mt_soc_playback_offload {
		compatible = "mediatek,mt_soc_offload_common";
	};

	mipi_rx_ana_csi0a: mipi_rx_ana_csi0a@11c10000 {
		compatible = "mediatek,mipi_rx_ana_csi0a", "syscon";
		reg = <0 0x11c10000 0 0x1000>;
		#clock-cells = <1>;
	};

	mipi_rx_ana_csi0b: mipi_rx_ana_csi0b@11c11000 {
		compatible = "mediatek,mipi_rx_ana_csi0b", "syscon";
		reg = <0 0x11c11000 0 0x1000>;
		#clock-cells = <1>;
	};

	mipi_rx_ana_csi1a: mipi_rx_ana_csi1a@11c12000 {
		compatible = "mediatek,mipi_rx_ana_csi1a", "syscon";
		reg = <0 0x11c12000 0 0x1000>;
		#clock-cells = <1>;
	};

	mipi_rx_ana_csi1b: mipi_rx_ana_csi1b@11c13000 {
		compatible = "mediatek,mipi_rx_ana_csi1b", "syscon";
		reg = <0 0x11c13000 0 0x1000>;
		#clock-cells = <1>;
	};

	mipi_rx_ana_csi2a: mipi_rx_ana_csi2a@11c14000 {
		compatible = "mediatek,mipi_rx_ana_csi2a", "syscon";
		reg = <0 0x11c14000 0 0x1000>;
		#clock-cells = <1>;
	};

	mipi_rx_ana_csi2b: mipi_rx_ana_csi2b@11c15000 {
		compatible = "mediatek,mipi_rx_ana_csi2b", "syscon";
		reg = <0 0x11c15000 0 0x1000>;
		#clock-cells = <1>;
	};

	mipi_tx0@11c80000 {
		compatible = "mediatek,mipi_tx0";
		reg = <0 0x11c80000 0 0x10000>;
	};

	efusec@11ce0000 {
		compatible = "mediatek,efusec";
		reg = <0 0x11ce0000 0 0x10000>;
	};

	mfg_cfg: mfg_cfg@13000000 {
		compatible = "mediatek,mfgcfg", "syscon";
		reg = <0 0x13000000 0 0x1000>;
		#clock-cells = <1>;
	};

	mali@13040000 {
		compatible = "mediatek,mali", "arm,mali-midgard", "arm,mali-bifrost";
		reg = <0 0x13040000 0 0x4000>;
		interrupts =
			<GIC_SPI 274 IRQ_TYPE_LEVEL_LOW>,
			<GIC_SPI 275 IRQ_TYPE_LEVEL_LOW>,
			<GIC_SPI 276 IRQ_TYPE_LEVEL_LOW>,
			<GIC_SPI 277 IRQ_TYPE_LEVEL_LOW>,
			<GIC_SPI 278 IRQ_TYPE_LEVEL_LOW>;
		interrupt-names =
			"GPU",
			"MMU",
			"JOB",
			"EVENT",
			"PWR";
	};

	gpufreq {
		compatible = "mediatek,mt6768-gpufreq";
		clocks =
			<&topckgen CLK_TOP_MFG_SEL>,	   /* clk_mux */
			<&topckgen CLK_TOP_MFGPLL>,        /* gpupll  */
			<&topckgen CLK_TOP_SYSPLL_D3>,     /* syspll_d3, 364Mhz */
			<&mfg_cfg CLK_MFGCFG_BG3D>,
			<&scpsys SCP_SYS_MFG_ASYNC>,
			<&scpsys SCP_SYS_MFG>,
			<&scpsys SCP_SYS_MFG_CORE0>,
			<&scpsys SCP_SYS_MFG_CORE1>;
		clock-names =
			"clk_mux",
			"clk_main_parent",
			"clk_sub_parent",
			"subsys_mfg_cg",
			"mtcmos_mfg_async",
			"mtcmos_mfg",
			"mtcmos_mfg_core0",
			"mtcmos_mfg_core1";
	};

	mmsys_config: mmsys_config@14000000 {
		compatible = "mediatek,mmsys_config", "syscon";
		reg = <0 0x14000000 0 0x1000>;
		interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_LOW>;
		#clock-cells = <1>;
		clocks = <&mmsys_config CLK_MM_CAM_MDP>,
				<&mmsys_config CLK_MM_IMG_DL_RELAY>,
				<&mmsys_config CLK_MM_IMG_DL_ASYNC_TOP>;
		clock-names = "CAM_MDP", "IMG_DL_RELAY", "IMG_DL_ASYNC_TOP";
	};

	disp_mutex0: disp_mutex0@14001000 {
		compatible = "mediatek,disp_mutex0";
		reg = <0 0x14001000 0 0x1000>;
		interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>;
	};

	smi_common@14002000 {
		compatible = "mediatek,smi_common";
		reg = <0 0x14002000 0 0x1000>;
		mediatek,smi-id = <5>;
		clocks = <&scpsys SCP_SYS_DIS>,
		       <&mmsys_config CLK_MM_SMI_COMM0>,
		       <&mmsys_config CLK_MM_SMI_COMM1>,
		       <&mmsys_config CLK_MM_SMI_COMMON>;
		clock-names = "scp-dis", "mm-comm0", "mm-comm1", "mm-common";
		mmsys_config = <&mmsys_config>;
	};

	mmdvfs_pmqos {
		compatible = "mediatek,mmdvfs_pmqos";
		mm_step0 = <457 1 0 3>;
		mm_step1 = <312 1 0 4>;
		mm_step2 = <228 1 0 5>;
		venc_step0 = <457 1 1 3>;
		venc_step1 = <416 1 1 6>;
		venc_step2 = <312 1 1 4>;
		cam_step0 = <546 1 2 7>;
		cam_step1 = <312 1 2 4>;
		cam_step2 = <228 1 2 5>;
		vopp_steps = <0 1 3>;
		disp_freq = "mm_step0", "mm_step1", "mm_step2";
		mdp_freq = "mm_step0", "mm_step1", "mm_step2";
		cam_freq = "cam_step0","cam_step1","cam_step2";
		img_freq = "mm_step0","mm_step1","mm_step2";
		vdec_freq = "mm_step0","mm_step1","mm_step2";
		venc_freq = "venc_step0","venc_step1","venc_step2";
		clocks = <&topckgen CLK_TOP_MM_SEL>,	/* 0 */
			<&topckgen CLK_TOP_VENC_SEL>,		/* 1 */
			<&topckgen CLK_TOP_CAM_SEL>,		/* 2 */
			<&topckgen CLK_TOP_MMPLL>,			/* 3 */
			<&topckgen CLK_TOP_UNIVPLL1_D2>,	/* 4 */
			<&topckgen CLK_TOP_MMPLL_D2>,		/* 5 */
			<&topckgen CLK_TOP_UNIVPLL_D3>,		/* 6 */
			<&topckgen CLK_TOP_SYSPLL_D2>;		/* 7 */
		clock-names = "mmdvfs_clk_mm_sel_ck",	/* 0 */
			"mmdvfs_clk_venc_sel_ck",			/* 1 */
			"mmdvfs_clk_cam_sel_ck",			/* 2 */
			"mmdvfs_clk_mmpll_ck",				/* 3 */
			"mmdvfs_clk_univpll1_d2_ck",		/* 4 */
			"mmdvfs_clk_mmpll_d2_ck",			/* 5 */
			"mmdvfs_clk_univpll_d3_ck",			/* 6 */
			"mmdvfs_clk_syspll_d2_ck";			/* 7 */
	};

	smi_larb0: smi_larb0@14003000 {
		compatible = "mediatek,smi_larb0", "mediatek,smi_larb";
		reg = <0 0x14003000 0 0x1000>;
		mediatek,smi-id = <0>;
		clocks = <&scpsys SCP_SYS_DIS>,
		       <&mmsys_config CLK_MM_SMI_LARB0>;
		clock-names = "scp-dis", "mm-larb0";
	};

	mdp_rdma0: mdp_rdma0@14004000 {
		compatible = "mediatek,mdp_rdma0";
		reg = <0 0x14004000 0 0x1000>;
		interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&mmsys_config CLK_MM_MDP_RDMA0>;
		clock-names = "MDP_RDMA0";
	};

	mdp_ccorr: mdp_ccorr0@14005000 {
		compatible = "mediatek,mdp_ccorr0";
		reg = <0 0x14005000 0 0x1000>;
		interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&mmsys_config CLK_MM_MDP_CCORR0>;
		clock-names = "MDP_CCORR";
	};

	mdp_rsz0: mdp_rsz0@14006000 {
		compatible = "mediatek,mdp_rsz0";
		reg = <0 0x14006000 0 0x1000>;
		interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&mmsys_config CLK_MM_MDP_RSZ0>;
		clock-names = "MDP_RSZ0";
	};

	mdp_rsz1: mdp_rsz1@14007000 {
		compatible = "mediatek,mdp_rsz1";
		reg = <0 0x14007000 0 0x1000>;
		interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&mmsys_config CLK_MM_MDP_RSZ1>;
		clock-names = "MDP_RSZ1";
	};

	mdp_wdma0: mdp_wdma0@14008000 {
		compatible = "mediatek,mdp_wdma0";
		reg = <0 0x14008000 0 0x1000>;
		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&mmsys_config CLK_MM_MDP_WDMA0>;
		clock-names = "MDP_WDMA";
	};

	mdp_wrot0: mdp_wrot0@14009000 {
		compatible = "mediatek,mdp_wrot0";
		reg = <0 0x14009000 0 0x1000>;
		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&mmsys_config CLK_MM_MDP_WROT0>;
		clock-names = "MDP_WROT0";
	};

	mdp_tdshp0: mdp_tdshp0@1400a000 {
		compatible = "mediatek,mdp_tdshp0";
		reg = <0 0x1400a000 0 0x1000>;
		clocks = <&mmsys_config CLK_MM_MDP_TDSHP0>;
		clock-names = "MDP_TDSHP";
	};

	disp_ovl0@1400b000 {
		compatible = "mediatek,disp_ovl0";
		reg = <0 0x1400b000 0 0x1000>;
		interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_LOW>;
	};

	disp_rdma0@1400d000 {
		compatible = "mediatek,disp_rdma0";
		reg = <0 0x1400d000 0 0x1000>;
		interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
	};

	disp_wdma0@1400e000 {
		compatible = "mediatek,disp_wdma0";
		reg = <0 0x1400e000 0 0x1000>;
		interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
	};

	disp_color0: disp_color0@1400f000 {
		compatible = "mediatek,disp_color0";
		reg = <0 0x1400f000 0 0x1000>;
		interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&mmsys_config CLK_MM_DISP_COLOR0>;
		clock-names = "MDP_COLOR";
	};

	disp_ccorr0@14010000 {
		compatible = "mediatek,disp_ccorr0";
		reg = <0 0x14010000 0 0x1000>;
		interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
	};

	disp_aal0@14011000 {
		compatible = "mediatek,disp_aal0";
		reg = <0 0x14011000 0 0x1000>;
		interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
	};

	disp_gamma0@14012000 {
		compatible = "mediatek,disp_gamma0";
		reg = <0 0x14012000 0 0x1000>;
		interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;
	};

	disp_dither0@14013000 {
		compatible = "mediatek,disp_dither0";
		reg = <0 0x14013000 0 0x1000>;
		interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>;
	};

	dsi0@14014000 {
		compatible = "mediatek,dsi0";
		reg = <0 0x14014000 0 0x1000>;
		interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_LOW>;
	};

	disp_ovl0_2l@1400c000 {
		compatible = "mediatek,disp_ovl0_2l";
		reg = <0 0x1400c000 0 0x1000>;
		interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_LOW>;
	};

	disp_rsz0@14015000 {
		compatible = "mediatek,disp_rsz0";
		reg = <0 0x14015000 0 0x1000>;
		interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_LOW>;
	};

	mtkfb: mtkfb@0 {
		compatible = "mediatek,mtkfb";
	};

	dispsys {
		compatible = "mediatek,dispsys";
		mediatek,larb = <&smi_larb0>;
		clocks = <&scpsys SCP_SYS_DIS>,
			<&mmsys_config CLK_MM_SMI_COMMON>,
			<&mmsys_config CLK_MM_SMI_LARB0>,
			<&mmsys_config CLK_MM_SMI_COMM0>,
			<&mmsys_config CLK_MM_SMI_COMM1>,
			<&mmsys_config CLK_MM_DISP_OVL0>,
			<&mmsys_config CLK_MM_DISP_OVL0_2L>,
			<&mmsys_config CLK_MM_DISP_RDMA0>,
			<&mmsys_config CLK_MM_DISP_WDMA0>,
			<&mmsys_config CLK_MM_DISP_COLOR0>,
			<&mmsys_config CLK_MM_DISP_CCORR0>,
			<&mmsys_config CLK_MM_DISP_AAL0>,
			<&mmsys_config CLK_MM_DISP_GAMMA0>,
			<&mmsys_config CLK_MM_DISP_DITHER0>,
			<&mmsys_config CLK_MM_DSI0>,
			<&mmsys_config CLK_MM_DIG_DSI>,
			<&mmsys_config CLK_MM_IMG_DL_RELAY>,
			<&mmsys_config CLK_MM_F26M_HRTWT>,
			<&mmsys_config CLK_MM_DISP_RSZ0>,
			<&apmixed CLK_APMIXED_MIPID0_26M>,
			<&topckgen CLK_TOP_DISP_PWM_SEL>,
			<&infracfg_ao CLK_IFR_DISP_PWM>,
			<&clk26m>,
			<&topckgen CLK_TOP_UNIVPLL2_D4>,
			<&topckgen CLK_TOP_ULPOSC1_D2>,
			<&topckgen CLK_TOP_ULPOSC1_D8>;

		clock-names = "MMSYS_MTCMOS",
			"MMSYS_SMI_COMMON",
			"MMSYS_SMI_LARB0",
			"MMSYS_GALS_COMM0",
			"MMSYS_GALS_COMM1",
			"MMSYS_DISP_OVL0",
			"MMSYS_DISP_OVL0_2L",
			"MMSYS_DISP_RDMA0",
			"MMSYS_DISP_WDMA0",
			"MMSYS_DISP_COLOR0",
			"MMSYS_DISP_CCORR0",
			"MMSYS_DISP_AAL0",
			"MMSYS_DISP_GAMMA0",
			"MMSYS_DISP_DITHER0",
			"MMSYS_DSI0_MM_CK",
			"MMSYS_DSI0_IF_CK",
			"MMSYS_IMG_DL_RELAY",
			"MMSYS_26M",
			"MMSYS_DISP_RSZ0",
			"APMIXED_MIPI_26M",
			"TOP_MUX_DISP_PWM",
			"DISP_PWM",
			"TOP_26M",
			"TOP_UNIVPLL2_D4",
			"TOP_ULPOSC1_D2",
			"TOP_ULPOSC1_D8";
	};

	dsi_te: dsi_te {
		compatible = "mediatek, dsi_te-eint";
		status = "disabled";
	};

	mm_mutex@14016000 {
		compatible = "mediatek,mm_mutex";
		reg = <0 0x14016000 0 0x1000>;
	};

	imgsys: imgsys@15020000 {
		compatible = "mediatek,imgsys", "syscon";
		reg = <0 0x15020000 0 0x1000>;
		#clock-cells = <1>;
		/* Camera CCF */
		clocks = <&scpsys SCP_SYS_DIS>,
			<&scpsys SCP_SYS_ISP>,
			<&scpsys SCP_SYS_CAM>,
			<&imgsys CLK_IMG_DIP>,
			<&camsys CLK_CAM>,
			<&camsys CLK_CAMTG>,
			<&camsys CLK_CAM_SENINF>,
			<&camsys CLK_CAMSV0>,
			<&camsys CLK_CAMSV1>,
			<&camsys CLK_CAMSV2>;
		clock-names = "ISP_SCP_SYS_DIS",
			"ISP_SCP_SYS_ISP",
			"ISP_SCP_SYS_CAM",
			"ISP_CLK_IMG_DIP",
			"ISP_CLK_CAM",
			"ISP_CLK_CAMTG",
			"ISP_CLK_CAM_SENINF",
			"ISP_CLK_CAMSV0",
			"ISP_CLK_CAMSV1",
			"ISP_CLK_CAMSV2";
	};

	dip1@15022000 {
		compatible = "mediatek,dip1";
		reg = <0 0x15022000 0 0x3000>;
		interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_LOW>;
	};
	fdvt@1502b000 {
		compatible = "mediatek,fdvt";
		reg = <0 0x1502b000 0 0x1000>;
		interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&imgsys CLK_IMG_FDVT>;
		clock-names = "FD_CLK_IMG_FDVT";
	};

	dpe@15028000 {
		compatible = "mediatek,dpe";
		reg = <0 0x15028000 0 0x1000>;
		interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&imgsys CLK_IMG_DPE>;
		clock-names = "DPE_CG_IMG_DPE";
	};

	smi_larb2: smi_larb2@15021000 {
		compatible = "mediatek,smi_larb2", "mediatek,smi_larb";
		reg = <0 0x15021000 0 0x1000>;
		mediatek,smi-id = <2>;
		clocks = <&scpsys SCP_SYS_ISP>,
			<&mmsys_config CLK_MM_SMI_IMG>, <&imgsys CLK_IMG_LARB2>;
		clock-names = "scp-isp", "mm-img", "img-larb2";
	};

	vcu: vcu@16000000 {
		compatible = "mediatek-vcu";
		mediatek,vcuid = <0>;
		mediatek,vcuname = "vcu";
		reg = <0 0x16000000 0 0x40000>,	    /* VDEC_BASE */
			 <0 0x17020000 0 0x10000>,  /* VENC_BASE */
			 <0 0x19002000 0 0x1000>;   /* VENC_LT */
#ifdef CONFIG_MTK_IOMMU_V2
		iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>;
#endif
		mediatek,mailbox-gce = <&gce_mbox>;
		mboxes = <&gce_mbox 1 0 CMDQ_THR_PRIO_1>,
			<&gce_mbox 5 0 CMDQ_THR_PRIO_1>;
		gce-event-names = "venc_eof",
			"venc_cmdq_pause_done",
			"venc_mb_done",
			"venc_128B_cnt_done";

		gce-events =  <&gce_mbox CMDQ_EVENT_VENC_FRAME_DONE>,
			<&gce_mbox CMDQ_EVENT_VENC_PAUSE_DONE>,
			<&gce_mbox CMDQ_EVENT_VENC_MB_DONE>,
			<&gce_mbox CMDQ_EVENT_VENC_128BYTE_CNT_DONE>;

	};

	vdec_gcon: vdec_gcon@16000000 {
		compatible = "mediatek,vdec_gcon", "syscon";
		reg = <0 0x16000000 0 0x1000>,		/* VDEC_SYS */
			 <0 0x16025000 0 0x1000>;		/* VDEC_MISC */
#ifdef CONFIG_MTK_IOMMU_V2
		iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>;
#endif
		mediatek,larb = <&smi_larb1>;
		interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_LOW>;
		mediatek,vcu = <&vcu>;

		clocks =
			<&scpsys SCP_SYS_DIS>,
			<&scpsys SCP_SYS_VDEC>,
			<&vdec_gcon CLK_VDEC_CKEN>;
		clock-names =
			"MT_SCP_SYS_DIS",
			"MT_SCP_SYS_VDE",
			"MT_CG_VDEC";
		#clock-cells = <1>;
	};

	smi_larb1: smi_larb1@16010000 {
		compatible = "mediatek,smi_larb1", "mediatek,smi_larb";
		reg = <0 0x16010000 0 0x1000>;
		interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_LOW>;
		mediatek,smi-id = <1>;
		clocks = <&scpsys SCP_SYS_VDEC>,
			<&mmsys_config CLK_MM_SMI_VDEC>,
			<&vdec_gcon CLK_VDEC_LARB1_CKEN>;
		clock-names = "scp-vdec", "mm-vdec", "vdec-larb1";
	};

	vdec@16020000 {
		compatible = "mediatek,vdec";
		reg = <0 0x16020000 0 0x10000>;
		interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_LOW>;
	};

	reserve@16030000 {
		compatible = "mediatek,reserve";
		reg = <0 0x16030000 0 0x10000>;
	};

	vdec_mbist_ctrl@16001000 {
		compatible = "mediatek,vdec_mbist_ctrl";
		reg = <0 0x16001000 0 0x1000>;
	};

	venc_gcon: venc_gcon@17000000 {
		compatible = "mediatek,venc_gcon", "syscon";
		reg = <0 0x17000000 0 0x1000>,
			<0 0x17020000 0 0x1000>;
#ifdef CONFIG_MTK_IOMMU_V2
		iommus = <&iommu M4U_PORT_VENC_RD_COMV>;
#endif
		mediatek,larb = <&smi_larb4>;
		interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_LOW>;
		mediatek,vcu = <&vcu>;

		clocks =
			<&scpsys SCP_SYS_DIS>,
			<&scpsys SCP_SYS_VENC>,
			<&venc_gcon CLK_VENC_SET1_VENC>;
		clock-names =
			"MT_SCP_SYS_DIS",
			"MT_SCP_SYS_VEN",
			"MT_CG_VENC";
		#clock-cells = <1>;
	};

	smi_larb4: smi_larb4@17010000 {
		compatible = "mediatek,smi_larb4", "mediatek,smi_larb";
		reg = <0 0x17010000 0 0x1000>;
		mediatek,smi-id = <4>;
		clocks = <&scpsys SCP_SYS_VENC>,
		       <&mmsys_config CLK_MM_SMI_VENC>,
		       <&venc_gcon CLK_VENC_SET1_VENC>,
		       <&venc_gcon CLK_VENC_SET2_JPGENC>;
		clock-names = "scp-venc", "mm-venc", "venc-venc", "venc-jpgenc";
	};

#ifdef CONFIG_MTK_IOMMU_V2
	ion: iommu {
		compatible = "mediatek,ion";
		iommus = <&iommu M4U_PORT_DISP_RDMA0>;
	};

	pseudo_m4u {
		compatible = "mediatek,mt-pseudo_m4u";
		iommus = <&iommu M4U_PORT_DISP_RDMA0>;
	};

	pseudo_m4u-larb0 {
		compatible = "mediatek,mt-pseudo_m4u-port";
		mediatek,larbid = <0>;
		iommus = <&iommu M4U_PORT_DISP_OVL0>,
			 <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>,
			 <&iommu M4U_PORT_DISP_RDMA0>,
			 <&iommu M4U_PORT_DISP_WDMA0>,
			 <&iommu M4U_PORT_MDP_RDMA0>,
			 <&iommu M4U_PORT_MDP_WDMA0>,
			 <&iommu M4U_PORT_MDP_WROT0>,
			 <&iommu M4U_PORT_DISP_FAKE0>;
	};

	pseudo_m4u-larb1 {
		compatible = "mediatek,mt-pseudo_m4u-port";
		mediatek,larbid = <1>;
		iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
			 <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
			 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
			 <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>,
			 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
			 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
			 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
			 <&iommu M4U_PORT_HW_VDEC_PPWRAP_EXT>,
			 <&iommu M4U_PORT_HW_VDEC_TILE_EXT>;
	};

	pseudo_m4u-larb2 {
		compatible = "mediatek,mt-pseudo_m4u-port";
		mediatek,larbid = <2>;
		iommus = <&iommu M4U_PORT_CAM_IMGI>,
			 <&iommu M4U_PORT_CAM_IMG2O>,
			 <&iommu M4U_PORT_CAM_IMG3O>,
			 <&iommu M4U_PORT_CAM_VIPI>,
			 <&iommu M4U_PORT_CAM_LCEI>,
			 <&iommu M4U_PORT_CAM_FD_RP>,
			 <&iommu M4U_PORT_CAM_FD_WR>,
			 <&iommu M4U_PORT_CAM_FD_RB>,
			 <&iommu M4U_PORT_CAM_DPE_RDMA>,
			 <&iommu M4U_PORT_CAM_DPE_WDMA>,
			 <&iommu M4U_PORT_CAM_RSC_RDMA>,
			 <&iommu M4U_PORT_CAM_RSC_WDMA>;
	};

	pseudo_m4u-larb3 {
		compatible = "mediatek,mt-pseudo_m4u-port";
		mediatek,larbid = <3>;
		iommus = <&iommu M4U_PORT_CAM_IMGO>,
			<&iommu M4U_PORT_CAM_RRZO>,
			<&iommu M4U_PORT_CAM_AAO>,
			<&iommu M4U_PORT_CAM_AFO>,
			<&iommu M4U_PORT_CAM_LSCI0>,
			<&iommu M4U_PORT_CAM_LSCI1>,
			<&iommu M4U_PORT_CAM_PDO>,
			<&iommu M4U_PORT_CAM_BPCI>,
			<&iommu M4U_PORT_CAM_LCSO>,
			<&iommu M4U_PORT_CAM_RSSO_A>,
			<&iommu M4U_PORT_CAM_RSSO_B>,
			<&iommu M4U_PORT_CAM_UFEO>,
			<&iommu M4U_PORT_CAM_SOC0>,
			<&iommu M4U_PORT_CAM_SOC1>,
			<&iommu M4U_PORT_CAM_SOC2>,
			<&iommu M4U_PORT_CAM_CCUI>,
			<&iommu M4U_PORT_CAM_CCUO>,
			<&iommu M4U_PORT_CAM_CACI>,
			<&iommu M4U_PORT_CAM_RAWI_A>,
			<&iommu M4U_PORT_CAM_RAWI_B>,
			<&iommu M4U_PORT_CAM_CCUG>;
	};

	pseudo_m4u-larb4 {
		compatible = "mediatek,mt-pseudo_m4u-port";
		mediatek,larbid = <4>;
		iommus = <&iommu M4U_PORT_VENC_RCPU>,
			<&iommu M4U_PORT_VENC_REC>,
			<&iommu M4U_PORT_VENC_BSDMA>,
			<&iommu M4U_PORT_VENC_SV_COMV>,
			<&iommu M4U_PORT_VENC_RD_COMV>,
			<&iommu M4U_PORT_JPGENC_RDMA>,
			<&iommu M4U_PORT_JPGENC_BSDMA>,
			<&iommu M4U_PORT_VENC_CUR_LUMA>,
			<&iommu M4U_PORT_VENC_CUR_CHROMA>,
			<&iommu M4U_PORT_VENC_REF_LUMA>,
			<&iommu M4U_PORT_VENC_REF_CHROMA>;
	};

	pseudo_m4u-ccu {
		compatible = "mediatek,mt-pseudo_m4u-port";
		mediatek,larbid = <CCU_PSEUDO_LARBID>;
		iommus = <&iommu M4U_PORT_CAM_CCUG>,
			<&iommu M4U_PORT_CAM_CCUO>,
			<&iommu M4U_PORT_CAM_CCUI>;
	};

	pseudo_m4u-misc {
		compatible = "mediatek,mt-pseudo_m4u-port";
		mediatek,larbid = <MISC_PSEUDO_LARBID>;
		iommus = <&iommu M4U_PORT_DISP_FAKE0>;
	};

#endif
	venc@17020000 {
		compatible = "mediatek,venc";
		reg = <0 0x17020000 0 0x10000>;
		interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_LOW>;
	};

	venc_jpg@17030000 {
		compatible = "mediatek,venc_jpg";
		reg = <0 0x17030000 0 0x10000>;
		interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_LOW>;
		clocks =
			<&venc_gcon CLK_VENC_SET2_JPGENC>;
		clock-names =
			"MT_CG_VENC_JPGENC";
	};

	mbist@17040000 {
		compatible = "mediatek,mbist";
		reg = <0 0x17040000 0 0x10000>;
	};

	mbist@17050000 {
		compatible = "mediatek,mbist";
		reg = <0 0x17050000 0 0x10000>;
	};

	mbist@17060000 {
		compatible = "mediatek,mbist";
		reg = <0 0x17060000 0 0x10000>;
	};

	mbist@17070000 {
		compatible = "mediatek,mbist";
		reg = <0 0x17070000 0 0x10000>;
	};

	wifi@18000000 {
		compatible = "mediatek,wifi";
		reg = <0 0x18000000 0 0x100000>;
		interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_LOW>;
		memory-region = <&wifi_mem>;
	};

	camsys: camsys@1a000000 {
		compatible = "mediatek,camsys", "syscon";
		reg = <0 0x1a000000  0 0x1000>;
		#clock-cells = <1>;
	};

	smi_larb3: smi_larb3@1a002000 {
		compatible = "mediatek,smi_larb3", "mediatek,smi_larb";
		reg = <0 0x1a002000 0 0x1000>;
		mediatek,smi-id = <3>;
		clocks = <&scpsys SCP_SYS_CAM>, <&mmsys_config CLK_MM_SMI_CAM>,
			<&camsys CLK_CAM_LARB3>;
		clock-names = "scp-cam", "mm-cam", "cam-larb3";
	};

	cam1@1a003000 {
		compatible = "mediatek,cam1";
		reg = <0 0x1a003000 0 0x1000>;
		interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_LOW>;
	};

	cam2@1a004000  {
		compatible = "mediatek,cam2";
		reg = <0 0x1a004000  0 0x1000>;
		interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_LOW>;
	};

	cam3@1a005000 {
		compatible = "mediatek,cam3";
		reg = <0 0x1a005000 0 0x1000>;
		interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_LOW>;
	};

	cam_set@1a00b000 {
		compatible = "mediatek,cam_set";
		reg = <0 0x1a00b000 0 0x1000>;
	};

	cama_set@1a00c000 {
		compatible = "mediatek,cama_set";
		reg = <0 0x1a00c000 0 0x1000>;
	};

	camb_set@1a00d000 {
		compatible = "mediatek,camb_set";
		reg = <0 0x1a00d000 0 0x1000>;
	};

	cam_inner@1a013000 {
		compatible = "mediatek,cam_inner";
		reg = <0 0x1a013000 0 0x1000>;
	};

	cama_inner@1a014000 {
		compatible = "mediatek,cama_inner";
		reg = <0 0x1a014000 0 0x1000>;
	};

	camb_inner@1a015000 {
		compatible = "mediatek,camb_inner";
		reg = <0 0x1a015000 0 0x1000>;
	};

	cam_clear@1a01b000 {
		compatible = "mediatek,cam_clear";
		reg = <0 0x1a01b000 0 0x1000>;
	};

	cama_clear@1a01c000 {
		compatible = "mediatek,cama_clear";
		reg = <0 0x1a01c000 0 0x1000>;
	};

	camb_clear@1a01d000 {
		compatible = "mediatek,camb_clear";
		reg = <0 0x1a01d000 0 0x1000>;
	};

	cama_ext@1a024000 {
		compatible = "mediatek,cama_ext";
		reg = <0 0x1a024000 0 0x1000>;
	};

	camb_ext@1a025000 {
		compatible = "mediatek,camb_ext";
		reg = <0 0x1a025000 0 0x1000>;
	};

	seninf1@1a040000 {
		compatible = "mediatek,seninf1";
		reg = <0 0x1a040000 0 0x1000>;
	};

	seninf2@1a041000 {
		compatible = "mediatek,seninf2";
		reg = <0 0x1a041000 0 0x1000>;
	};

	seninf3@1a042000 {
		compatible = "mediatek,seninf3";
		reg = <0 0x1a042000 0 0x1000>;
	};

	seninf4@1a043000 {
		compatible = "mediatek,seninf4";
		reg = <0 0x1a043000 0 0x1000>;
	};

	kd_camera_hw1: kd_camera_hw1@1a040000 {
		compatible = "mediatek,camera_hw";
		reg = <0 0x1a040000 0 0x1000>;
		/* SENINF_ADDR */
		/* Camera Common Clock Framework (CCF) */
		clocks = <&topckgen CLK_TOP_CAMTG_SEL>,
		<&topckgen CLK_TOP_CAMTG1_SEL>,
		<&topckgen CLK_TOP_CAMTG2_SEL>,
		<&topckgen CLK_TOP_CAMTG3_SEL>,
		<&topckgen CLK_TOP_USB20_192M_D32>,
		<&topckgen CLK_TOP_USB20_192M_D16>,
		<&topckgen CLK_TOP_UNIVPLL2_D32>,
		<&topckgen CLK_TOP_USB20_192M_D4>,
		<&topckgen CLK_TOP_UNIVPLL2_D8>,
		<&topckgen CLK_TOP_USB20_192M_D8>,
		<&clk26m>,
		<&camsys CLK_CAM_SENINF>,
		<&apmixed CLK_APMIXED_MIPIC0_26M>,
		<&apmixed CLK_APMIXED_MIPIC1_26M>,
		<&mipi_rx_ana_csi0a CLK_MIPI0A_CSR_CSI_EN_0A>,
		<&mipi_rx_ana_csi0b CLK_MIPI0B_CSR_CSI_EN_0B>,
		<&mipi_rx_ana_csi1a CLK_MIPI1A_CSR_CSI_EN_1A>,
		<&mipi_rx_ana_csi1b CLK_MIPI1B_CSR_CSI_EN_1B>,
		<&mipi_rx_ana_csi2a CLK_MIPI2A_CSR_CSI_EN_2A>,
		<&mipi_rx_ana_csi2b CLK_MIPI2B_CSR_CSI_EN_2B>,
		<&topckgen CLK_TOP_CAMTM_SEL>,
		<&topckgen CLK_TOP_UNIVPLL2_D2>,
		<&scpsys SCP_SYS_CAM>;


		clock-names = "CLK_TOP_CAMTG_SEL",
			"CLK_TOP_CAMTG1_SEL",
			"CLK_TOP_CAMTG2_SEL",
			"CLK_TOP_CAMTG3_SEL",
			"CLK_MCLK_6M",
			"CLK_MCLK_12M",
			"CLK_MCLK_13M",
			"CLK_MCLK_48M",
			"CLK_MCLK_52M",
			"CLK_MCLK_24M",
			"CLK_MCLK_26M",
			"CLK_CAM_SENINF_CG",
			"CLK_MIPI_C0_26M_CG",
			"CLK_MIPI_C1_26M_CG",
			"CLK_MIPI_ANA_0A_CG",
			"CLK_MIPI_ANA_0B_CG",
			"CLK_MIPI_ANA_1A_CG",
			"CLK_MIPI_ANA_1B_CG",
			"CLK_MIPI_ANA_2A_CG",
			"CLK_MIPI_ANA_2B_CG",
			"CLK_TOP_CAMTM_SEL_CG",
			"CLK_TOP_CAMTM_208_CG",
			"CLK_SCP_SYS_CAM";
	};

	flashlight_core: flashlight_core {
		compatible = "mediatek,flashlight_core";
	};

	flashlights_led191: flashlights_led191 {
		compatible = "mediatek,flashlights_led191";
		decouple = <0>;
		channel@1 {
			type = <0>;
			ct = <0>;
			part = <0>;
		};
		channel@2 {
			type = <0>;
			ct = <1>;
			part = <0>;
		};
	};
	flashlights_mt6370: flashlights_mt6370 {
		compatible = "mediatek,flashlights_mt6370";
		decouple = <0>;
		channel@1 {
			type = <0>;
			ct = <0>;
			part = <0>;
		};
		channel@2 {
			type = <0>;
			ct = <1>;
			part = <0>;
		};
	};

	camsv1@1a050000 {
		compatible = "mediatek,camsv1";
		reg = <0 0x1a050000 0 0x1000>;
		interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_LOW>;
	};

	camsv2@1a051000 {
		compatible = "mediatek,camsv2";
		reg = <0 0x1a051000 0 0x1000>;
		interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_LOW>;
	};

	camsv3@1a052000 {
		compatible = "mediatek,camsv3";
		reg = <0 0x1a052000 0 0x1000>;
		interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_LOW>;
	};

	camsv4@1a053000 {
		compatible = "mediatek,camsv4";
		reg = <0 0x1a053000 0 0x1000>;
		interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_LOW>;
	};

	ccu@1a0b1000 {
		compatible = "mediatek,ccu";
		reg = <0 0x1a0b1000 0 0x10000>;
		interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&camsys CLK_CAM_CCU>,
			<&scpsys SCP_SYS_CAM>;
		clock-names = "CCU_CLK_CAM_CCU",
			"CAM_PWR";
#ifdef CONFIG_MTK_IOMMU_V2
		iommus = <&iommu M4U_PORT_CAM_CCUG>;
#endif
	};

	/* ATF logger SW IRQ number 328  = 32 + 296 */
	atf_logger {
		compatible = "mediatek,atf_logger";
		interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>;
	};

	/* AMMS SW IRQ number GIC:99 DTS:67*/
	amms_control {
		compatible = "mediatek,amms";
		interrupts = <GIC_SPI 305 IRQ_TYPE_EDGE_RISING>;
	};

	odm: odm {
		compatible = "simple-bus";
		/* reserved for overlay by odm */
	};

	memory_ssmr_features: memory-ssmr-features {
		compatible = "mediatek,memory-ssmr-features";
		svp-size = <0 0x10000000>;
		iris-recognition-size = <0 0x10000000>;
		2d_fr-size = <0 0>;
		tui-size = <0 0x4000000>;
		wfd-size = <0 0x4000000>;
		prot-sharedmem-size = <0 0x8000000>;
		ta-elf-size = <0 0x1000000>;
		ta-stack-heap-size = <0 0x6000000>;
		sdsp-tee-sharedmem-size = <0 0x1000000>;
		sdsp-firmware-size = <0 0x1000000>;
	};

	radio_md_cfg: radio_md_cfg {
		compatible = "mediatek,radio_md_cfg";
	};



	mt_charger: mt_charger {
		compatible = "mediatek,mt-charger";
	};

	lk_charger: lk_charger {
		compatible = "mediatek,lk_charger";
		enable_anime;
		/* enable_pe_plus; */
		enable_pd20_reset;
		power_path_support;
		max_charger_voltage = <15000000>;
		fast_charge_voltage = <3000000>;

		/* charging current */
		usb_charger_current = <500000>;
		ac_charger_current = <2050000>;
		ac_charger_input_current = <3200000>;
		non_std_ac_charger_current = <500000>;
		charging_host_charger_current = <1500000>;
		ta_ac_charger_current = <3000000>;
		pd_charger_current = <500000>;

		/* battery temperature protection */
		temp_t4_threshold = <50>;
		temp_t3_threshold = <45>;
		temp_t1_threshold = <0>;
	};

	charger: charger {
		compatible = "mediatek,charger";
		algorithm_name = "SwitchCharging";
		/* enable_sw_jeita; */
		/* enable_pe_plus; */
		/* enable_pe_2; */
		/* enable_pe_3; */
		/* enable_pe_4; */
		enable_type_c;
		power_path_support;
		enable_dynamic_mivr;
		disable_pd_dual;

		/* common */
		battery_cv = <4350000>;
		max_charger_voltage = <15000000>;
		min_charger_voltage = <4600000>;

		/* dynamic mivr */
		min_charger_voltage_1 = <4400000>;
		min_charger_voltage_2 = <4200000>;
		max_dmivr_charger_current = <1400000>;

		/* charging current */
		usb_charger_current_suspend = <0>;
		usb_charger_current_unconfigured = <70000>;
		usb_charger_current_configured = <500000>;
		usb_charger_current = <500000>;
		ac_charger_current = <2050000>;
		ac_charger_input_current = <3200000>;
		non_std_ac_charger_current = <500000>;
		charging_host_charger_current = <1500000>;
		apple_1_0a_charger_current = <650000>;
		apple_2_1a_charger_current = <800000>;
		ta_ac_charger_current = <3000000>;

		/* sw jeita */
		jeita_temp_above_t4_cv = <4240000>;
		jeita_temp_t3_to_t4_cv = <4240000>;
		jeita_temp_t2_to_t3_cv = <4340000>;
		jeita_temp_t1_to_t2_cv = <4240000>;
		jeita_temp_t0_to_t1_cv = <4040000>;
		jeita_temp_below_t0_cv = <4040000>;
		temp_t4_thres = <50>;
		temp_t4_thres_minus_x_degree = <47>;
		temp_t3_thres = <45>;
		temp_t3_thres_minus_x_degree = <39>;
		temp_t2_thres = <10>;
		temp_t2_thres_plus_x_degree = <16>;
		temp_t1_thres = <0>;
		temp_t1_thres_plus_x_degree = <6>;
		temp_t0_thres = <0>;
		temp_t0_thres_plus_x_degree = <0>;
		temp_neg_10_thres = <0>;

		/* battery temperature protection */
		enable_min_charge_temp;
		min_charge_temp = <0>;
		min_charge_temp_plus_x_degree = <6>;
		max_charge_temp = <50>;
		max_charge_temp_minus_x_degree = <47>;


		/* PE */
		pe_ichg_level_threshold = <1000000>; /* uA */
		ta_ac_12v_input_current = <3200000>;
		ta_ac_9v_input_current = <3200000>;
		ta_ac_7v_input_current = <3200000>;

		/* PE 2.0 */
		pe20_ichg_level_threshold = <1000000>; /* uA */
		ta_start_battery_soc = <0>;
		ta_stop_battery_soc = <85>;

		/* PE 4.0 */
		high_temp_to_leave_pe40 = <46>;
		high_temp_to_enter_pe40 = <39>;
		low_temp_to_leave_pe40 = <10>;
		low_temp_to_enter_pe40 = <16>;

		/* PE 4.0 single charger*/
		pe40_single_charger_input_current = <3000000>;
		pe40_single_charger_current = <3000000>;

		/* PE 4.0 dual charger*/
		pe40_dual_charger_input_current = <3000000>;
		pe40_dual_charger_chg1_current = <2000000>;
		pe40_dual_charger_chg2_current = <2000000>;
		pe40_stop_battery_soc = <80>;

		/* PE 4.0 cable impedance (mohm) */
		pe40_r_cable_1a_lower = <518>;
		pe40_r_cable_2a_lower = <383>;
		pe40_r_cable_3a_lower = <245>;

		/* dual charger */
		chg1_ta_ac_charger_current = <1500000>;
		chg2_ta_ac_charger_current = <1500000>;
		slave_mivr_diff = <100000>;
		dual_polling_ieoc = <450000>;

		/* cable measurement impedance */
		cable_imp_threshold = <699>;
		vbat_cable_imp_threshold = <3900000>; /* uV */

		/* bif */
		bif_threshold1 = <4250000>;
		bif_threshold2 = <4300000>;
		bif_cv_under_threshold2 = <4450000>;

		/* PD */
		pd_vbus_low_bound = <5000000>;
		pd_vbus_upper_bound = <5000000>;
		pd_ichg_level_threshold = <1000000>; /* uA */
		pd_stop_battery_soc = <80>;

		ibus_err = <14>;
		vsys_watt = <5000000>;
	};

	pd_adapter: pd_adapter {
		compatible = "mediatek,pd_adapter";
		adapter_name = "pd_adapter";
	};

	rt9465_slave_chr: rt9465_slave_chr {
		compatible = "richtek,rt9465";
	};

	rt-pd-manager {
		compatible = "mediatek,rt-pd-manager";
	};

	subpmic_pmu_eint: mt6370_pmu_eint {
	};

	tcpc_pd: tcpc_pd_eint {
	};

	irtx_pwm:irtx_pwm {
		compatible = "mediatek,irtx-pwm";
		pwm_ch = <0>;
		pwm_data_invert = <0>;
	};

	pmic_clock_buffer_ctrl: pmic_clock_buffer_ctrl {
		compatible = "mediatek,pmic_clock_buffer";
		mediatek,clkbuf-quantity = <7>;
		mediatek,clkbuf-config = <2 1 1 2 0 0 0>;
		mediatek,clkbuf-driving-current = <1 1 1 1 1 1 1>;
	};

	touch: touch {
		compatible = "mediatek,touch";
	};
	xiaomi_touch{
		compatible = "xiaomi-touch";
		status = "ok";
		touch,name = "xiaomi-touch";
    };
/*
	nfc:nfc {
		compatible = "mediatek,nfc-gpio-v2";
		gpio-rst = <159>;
		gpio-rst-std = <&pio 159 0x0>;
		gpio-irq = <9>;
		gpio-irq-std = <&pio 9 0x0>;
	};*/

	irq_nfc: irq_nfc {
		compatible = "mediatek,irq_nfc-eint";
	};
	/* NFC end */

	smart_pa: smart_pa {
	};

    board_id: board_id {
		compatible = "mediatek,board_id";
	};

	blk_thermal: blk_thermal {
		compatible = "mediatek,blk_thermal_ntc";
		io-channels = <&auxadc 4>;
		io-channel-names = "blk_thermal-channel";
		status = "okay";
	};
	gpio_usage_mapping:gpio {
		compatible = "mediatek,gpio_usage_mapping";
	};

	md1_sim1_hot_plug_eint: md1_sim1_hot_plug_eint {
	};

	md1_sim2_hot_plug_eint: md1_sim2_hot_plug_eint {
	};
};

&i2c7 {
	speaker_amp: speaker_amp@34 {
		status = "disable";
	};
};

&pio {
	aud_clk_mosi_off: aud_clk_mosi_off {
		pins_cmd0_dat {
			pinmux = <PINMUX_GPIO136__FUNC_GPIO136>,
				 <PINMUX_GPIO137__FUNC_GPIO137>;
		};
	};

	aud_clk_mosi_on: aud_clk_mosi_on {
		pins_cmd0_dat {
			pinmux = <PINMUX_GPIO136__FUNC_AUD_CLK_MOSI>;
			input-schmitt-enable;
		};
		pins_cmd1_dat {
			pinmux = <PINMUX_GPIO137__FUNC_AUD_SYNC_MOSI>;
			input-schmitt-enable;
		};
	};

	aud_clk_miso_off: aud_clk_miso_off {
		pins_cmd0_dat {
			pinmux = <PINMUX_GPIO140__FUNC_GPIO140>,
				 <PINMUX_GPIO141__FUNC_GPIO141>;
		};
	};

	aud_clk_miso_on: aud_clk_miso_on {
		pins_cmd0_dat {
			pinmux = <PINMUX_GPIO140__FUNC_AUD_CLK_MISO>;
			input-schmitt-enable;
		};
		pins_cmd1_dat {
			pinmux = <PINMUX_GPIO141__FUNC_AUD_SYNC_MISO>;
			input-schmitt-enable;
		};
	};

	aud_dat_mosi_off: aud_dat_mosi_off {
		pins_cmd0_dat {
			pinmux = <PINMUX_GPIO136__FUNC_GPIO136>;
			input-enable;
			slew-rate = <0>;
			bias-disable;
		};
		pins_cmd1_dat {
			pinmux = <PINMUX_GPIO137__FUNC_GPIO137>;
			input-enable;
			slew-rate = <0>;
			bias-disable;
		};
		pins_cmd2_dat {
			pinmux = <PINMUX_GPIO138__FUNC_GPIO138>;
			input-enable;
			slew-rate = <0>;
			bias-disable;
		};
		pins_cmd3_dat {
			pinmux = <PINMUX_GPIO139__FUNC_GPIO139>;
			input-enable;
			slew-rate = <0>;
			bias-pull-down;
		};
	};

	aud_dat_mosi_on: aud_dat_mosi_on {
		pins_cmd0_dat {
			pinmux = <PINMUX_GPIO136__FUNC_AUD_CLK_MOSI>;
			//input-schmitt-enable;
			drive-strength = <3>;
		};
		pins_cmd1_dat {
			pinmux = <PINMUX_GPIO137__FUNC_AUD_SYNC_MOSI>;
			//input-schmitt-enable;
			drive-strength = <3>;
		};
		pins_cmd2_dat {
			pinmux = <PINMUX_GPIO138__FUNC_AUD_DAT_MOSI0>;
			//input-schmitt-enable;
			drive-strength = <3>;
		};
		pins_cmd3_dat {
			pinmux = <PINMUX_GPIO139__FUNC_AUD_DAT_MOSI1>;
			//input-schmitt-enable;
			drive-strength = <3>;
		};
	};

	aud_dat_miso_off: aud_dat_miso_off {
		pins_cmd0_dat {
			pinmux = <PINMUX_GPIO140__FUNC_GPIO140>;
			input-enable;
			slew-rate = <0>;
			bias-disable;
		};
		pins_cmd1_dat {
			pinmux = <PINMUX_GPIO141__FUNC_GPIO141>;
			input-enable;
			slew-rate = <0>;
			bias-disable;
		};
		pins_cmd2_dat {
			pinmux = <PINMUX_GPIO142__FUNC_GPIO142>;
			input-enable;
			slew-rate = <0>;
			bias-disable;
		};
		pins_cmd3_dat {
			pinmux = <PINMUX_GPIO143__FUNC_GPIO143>;
			input-enable;
			slew-rate = <0>;
			bias-disable;
		};
	};

	aud_dat_miso_on: aud_dat_miso_on {
		pins_cmd0_dat {
			pinmux = <PINMUX_GPIO140__FUNC_AUD_CLK_MISO>;
			//input-schmitt-enable;
			drive-strength = <3>;
		};
		pins_cmd1_dat {
			pinmux = <PINMUX_GPIO141__FUNC_AUD_SYNC_MISO>;
			//input-schmitt-enable;
			drive-strength = <3>;
		};
		pins_cmd2_dat {
			pinmux = <PINMUX_GPIO142__FUNC_AUD_DAT_MISO0>;
			//input-schmitt-enable;
			drive-strength = <3>;
		};
		pins_cmd3_dat {
			pinmux = <PINMUX_GPIO143__FUNC_AUD_DAT_MISO1>;
			//input-schmitt-enable;
			drive-strength = <3>;
		};
	};

	aud_gpio_i2s0_off: aud_gpio_i2s0_off {
		pins_cmd_dat {
			pinmux = <PINMUX_GPIO40__FUNC_GPIO40>;
		};
	};

	aud_gpio_i2s0_on: aud_gpio_i2s0_on {
		pins_cmd_dat {
			pinmux = <PINMUX_GPIO40__FUNC_I2S0_DI>;
		};
	};

	aud_gpio_i2s1_off: aud_gpio_i2s1_off {
	};

	aud_gpio_i2s1_on: aud_gpio_i2s1_on {
	};

	aud_gpio_i2s2_off: aud_gpio_i2s2_off {
	};

	aud_gpio_i2s2_on: aud_gpio_i2s2_on {
	};

	aud_gpio_i2s3_off: aud_gpio_i2s3_off {
		pins_cmd_dat {
			pinmux = <PINMUX_GPIO37__FUNC_GPIO37>,
				 <PINMUX_GPIO38__FUNC_GPIO38>,
				 <PINMUX_GPIO36__FUNC_GPIO36>;
		};
	};

	aud_gpio_i2s3_on: aud_gpio_i2s3_on {
		pins_cmd_dat {
			pinmux = <PINMUX_GPIO37__FUNC_I2S3_LRCK>,
				 <PINMUX_GPIO38__FUNC_I2S3_DO>,
				 <PINMUX_GPIO36__FUNC_I2S3_BCK>;
		};
	};

	vow_dat_miso_off: vow_dat_miso_off {
		pins_cmd1_dat {
			pinmux = <PINMUX_GPIO142__FUNC_GPIO142>;
		};
	};

	vow_dat_miso_on: vow_dat_miso_on {
		pins_cmd1_dat {
			pinmux = <PINMUX_GPIO142__FUNC_VOW_DAT_MISO>;
		};
	};

	vow_clk_miso_off: vow_clk_miso_off {
		pins_cmd3_dat {
			pinmux = <PINMUX_GPIO143__FUNC_GPIO143>;
		};
	};

	vow_clk_miso_on: vow_clk_miso_on {
		pins_cmd3_dat {
			pinmux = <PINMUX_GPIO143__FUNC_VOW_CLK_MISO>;
		};
	};


	reverse_high: reverse_high {
		pins_cmd_dat {
			pinmux = <PINMUX_GPIO91__FUNC_GPIO91>;
			slew-rate = <1>;
			output-high;
		};
	};

	reverse_low: reverse_low {
		pins_cmd_dat {
			pinmux = <PINMUX_GPIO91__FUNC_GPIO91>;
			slew-rate = <1>;
			output-low;
		};
	};
};

/* move shiva tp dts config to here to avoid boot up error */
#ifdef CONFIG_TARGET_PRODUCT_SHIVACOMMON
&spi0 {
	status = "ok";

	/* Novatek device tree node */
	novatek36672@0 {
	compatible = "novatek36672,NVT-ts-spi","focaltech8719P,FTS-ts-spi";
	reg = <0>; //Same as CS ID
	status = "ok";

	spi-max-frequency = <8000000>;	//4800000,9600000,15000000,19200000
	novatek,reset-gpio = <&pio 92 0x00>;
	novatek,irq-gpio = <&pio 1 0x2001>;

	/* 525 */
	//novatek,swrst-n8-addr = <0x01F01A>;

	/* 672A, 525B, 675, 526, 672C */
	novatek,swrst-n8-addr = <0x03F0FE>;
	novatek,spi-rd-fast-addr = <0x03F310>;

	/* MP */
		novatek,mp-support-dt;

		novatek-mp-criteria-5932@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "novatek-mp-criteria-5932";

			/* MP Config */
			IC_X_CFG_SIZE = <16>;
			IC_Y_CFG_SIZE = <36>;
			IC_KEY_CFG_SIZE = <4>;
			X_Channel = <16>;
			Y_Channel = <36>;
			AIN_X = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
			AIN_Y = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
						18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35>;
			AIN_KEY = <0 1 2 0xFF>;

			/* MP Criteria */
			PS_Config_Lmt_Short_Rawdata_P = <
				14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000
				14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000
				14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000
				14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000
				14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000
				14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000
				14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000
				14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000
				14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000
				14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000
				14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000
				14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000
				14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000
				14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000
				14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000
				14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000
				14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000
				14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000
				14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000
				14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000
				14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000
				14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000
				14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000
				14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000
				14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000
				14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000
				14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000
				14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000
				14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000
				14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000
				14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000
				14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000
				14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000
				14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000
				14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000
				14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000	14000
				14008 14008 14008>;

			PS_Config_Lmt_Short_Rawdata_N = <
				11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300
				11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300
				11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300
				11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300
				11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300
				11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300
				11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300
				11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300
				11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300
				11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300
				11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300
				11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300
				11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300
				11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300
				11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300
				11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300
				11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300
				11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300
				11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300
				11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300
				11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300
				11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300
				11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300
				11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300
				11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300
				11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300
				11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300
				11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300
				11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300
				11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300
				11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300
				11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300
				11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300
				11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300
				11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300
				11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300	11300
				10000 10000 10000>;

			PS_Config_Lmt_Open_Rawdata_P = <
				2674	4147	4159	4212	4166	4193	3576	65535	65535	3653	4213	4269	4239	4318	4215	2773
				4095	4182	4119	4177	4127	4160	4110	4264	4218	4207	4161	4208	4180	4257	4226	4231
				4204	4208	4147	4201	4151	4192	4141	4168	4168	4237	4194	4240	4216	4291	4253	4321
				4178	4212	4152	4208	4156	4197	4140	4166	4175	4241	4206	4249	4227	4297	4263	4310
				4201	4224	4168	4220	4160	4201	4146	4173	4194	4260	4226	4265	4246	4314	4276	4326
				4201	4230	4177	4229	4168	4208	4150	4174	4191	4254	4221	4262	4243	4309	4273	4330
				4211	4245	4187	4239	4179	4224	4163	4187	4206	4264	4236	4279	4258	4324	4288	4320
				4212	4246	4189	4239	4182	4225	4163	4187	4212	4268	4243	4287	4265	4328	4296	4324
				4221	4234	4178	4226	4171	4217	4154	4175	4210	4265	4240	4286	4260	4321	4287	4329
				4221	4243	4188	4232	4178	4222	4157	4184	4232	4272	4234	4296	4269	4325	4293	4324
				4203	4248	4196	4236	4178	4225	4159	4189	4234	4278	4239	4300	4277	4335	4297	4325
				4208	4253	4204	4246	4187	4231	4165	4196	4235	4278	4239	4301	4274	4330	4293	4324
				4208	4248	4198	4239	4182	4227	4159	4189	4231	4273	4239	4301	4272	4330	4295	4321
				4211	4257	4204	4244	4185	4232	4163	4201	4240	4282	4249	4311	4277	4334	4295	4307
				4202	4236	4197	4234	4174	4218	4151	4194	4237	4282	4248	4310	4276	4334	4288	4287
				4207	4243	4199	4239	4178	4222	4161	4201	4225	4265	4235	4296	4258	4320	4271	4284
				4193	4235	4192	4230	4170	4213	4152	4208	4204	4253	4222	4284	4249	4306	4253	4284
				4194	4224	4183	4222	4163	4208	4147	4201	4213	4253	4222	4283	4243	4302	4248	4287
				4188	4229	4183	4222	4163	4208	4147	4199	4207	4250	4221	4282	4239	4297	4244	4273
				4165	4224	4178	4218	4157	4204	4144	4196	4202	4241	4213	4273	4230	4290	4234	4272
				4168	4206	4156	4197	4137	4185	4126	4177	4191	4239	4204	4263	4220	4279	4218	4272
				4166	4192	4146	4183	4121	4166	4112	4157	4185	4237	4202	4259	4213	4276	4213	4260
				4149	4191	4140	4179	4117	4166	4113	4164	4180	4236	4201	4257	4213	4272	4217	4239
				4132	4179	4128	4168	4103	4152	4100	4151	4173	4231	4194	4251	4203	4262	4206	4236
				4130	4169	4121	4165	4103	4150	4099	4149	4156	4216	4173	4229	4184	4239	4184	4221
				4119	4150	4103	4145	4083	4133	4085	4133	4155	4212	4173	4229	4180	4236	4182	4212
				4108	4155	4103	4146	4083	4133	4084	4133	4136	4199	4155	4211	4165	4216	4163	4206
				4089	4131	4080	4119	4057	4114	4061	4112	4122	4185	4138	4192	4146	4199	4150	4191
				4094	4116	4062	4103	4041	4095	4044	4093	4116	4178	4133	4188	4145	4196	4147	4170
				4074	4099	4047	4089	4027	4080	4027	4076	4098	4159	4114	4171	4130	4180	4132	4157
				4058	4089	4033	4076	4017	4072	4023	4074	4072	4133	4089	4145	4103	4154	4107	4145
				3738	4081	3731	4070	3714	4064	3717	4062	3765	4126	3776	4136	3792	4142	3797	4128
				3736	3751	3699	3743	3685	3733	3689	3741	3754	3806	3765	3823	3782	3832	3788	3835
				3728	3737	3686	3731	3672	3719	3677	3724	3733	3785	3743	3802	3759	3810	3770	3864
				3610	3719	3667	3712	3655	3700	3663	3712	3718	3768	3727	3785	3740	3792	3752	3714
				2202	3661	3672	3721	3661	3708	3666	3716	3740	3787	3747	3808	3765	3813	3713	2301
				5120 5120 5120>;

			PS_Config_Lmt_Open_Rawdata_N = <
				1537	2384	2390	2421	2395	2410	2055	(-65535)	(-65535)	2100	2422	2454	2436	2482	2422	1594
				2354	2403	2368	2400	2372	2391	2363	2451	2425	2418	2392	2419	2403	2446	2429	2432
				2417	2419	2384	2414	2386	2409	2380	2395	2395	2436	2411	2437	2423	2466	2444	2484
				2401	2421	2387	2419	2389	2412	2379	2395	2400	2438	2417	2442	2430	2470	2450	2477
				2414	2427	2395	2425	2391	2414	2383	2398	2411	2449	2429	2452	2441	2479	2457	2487
				2414	2431	2400	2430	2395	2419	2385	2399	2409	2445	2426	2449	2438	2476	2456	2489
				2420	2440	2406	2436	2402	2427	2392	2406	2417	2451	2435	2460	2447	2485	2465	2483
				2421	2441	2408	2436	2403	2428	2392	2406	2421	2453	2438	2464	2452	2487	2469	2485
				2426	2433	2401	2429	2398	2424	2387	2400	2419	2452	2437	2463	2449	2484	2464	2488
				2426	2438	2407	2433	2401	2427	2390	2405	2433	2455	2433	2469	2454	2486	2468	2485
				2416	2441	2411	2435	2401	2428	2390	2408	2433	2459	2436	2471	2458	2492	2470	2486
				2419	2444	2417	2441	2406	2432	2394	2411	2434	2459	2436	2472	2457	2489	2468	2485
				2419	2441	2413	2436	2403	2430	2390	2408	2432	2456	2436	2472	2455	2489	2468	2484
				2420	2446	2417	2439	2406	2433	2392	2414	2437	2461	2442	2478	2458	2491	2468	2476
				2415	2435	2412	2433	2399	2425	2386	2411	2436	2461	2441	2477	2457	2491	2465	2464
				2418	2438	2414	2436	2401	2427	2392	2414	2428	2452	2434	2469	2447	2483	2454	2463
				2410	2434	2409	2431	2397	2422	2387	2419	2417	2444	2427	2463	2442	2475	2444	2463
				2411	2427	2404	2427	2392	2419	2384	2414	2422	2444	2427	2462	2438	2473	2441	2464
				2407	2430	2404	2427	2392	2419	2384	2414	2418	2443	2426	2461	2436	2470	2439	2456
				2394	2427	2401	2425	2390	2417	2381	2411	2415	2438	2422	2456	2431	2465	2433	2455
				2395	2417	2389	2412	2378	2406	2371	2400	2409	2436	2417	2450	2425	2460	2425	2455
				2395	2409	2383	2404	2368	2395	2363	2390	2406	2436	2415	2448	2422	2457	2422	2449
				2384	2409	2379	2402	2366	2395	2364	2393	2403	2435	2414	2446	2422	2455	2424	2436
				2375	2402	2373	2395	2358	2387	2357	2386	2398	2432	2411	2444	2416	2449	2417	2435
				2373	2396	2368	2394	2358	2385	2356	2384	2389	2423	2398	2430	2405	2436	2405	2426
				2368	2385	2358	2382	2346	2376	2348	2376	2388	2421	2398	2430	2403	2435	2403	2421
				2361	2388	2358	2383	2346	2376	2347	2376	2377	2414	2388	2420	2394	2423	2392	2417
				2350	2374	2345	2368	2332	2365	2334	2363	2369	2406	2379	2409	2383	2414	2385	2409
				2353	2365	2335	2358	2322	2354	2325	2352	2365	2401	2376	2407	2382	2411	2384	2397
				2341	2356	2326	2350	2314	2345	2314	2343	2355	2390	2365	2398	2373	2403	2375	2390
				2333	2350	2318	2343	2308	2341	2312	2341	2341	2376	2350	2382	2358	2387	2360	2382
				2149	2346	2144	2339	2135	2336	2136	2335	2164	2371	2171	2377	2179	2381	2182	2373
				2147	2156	2126	2152	2118	2146	2120	2150	2157	2187	2164	2198	2173	2203	2177	2204
				2143	2148	2119	2144	2111	2138	2114	2141	2146	2176	2152	2185	2160	2190	2167	2221
				2075	2138	2108	2133	2100	2127	2106	2133	2137	2165	2142	2176	2149	2179	2157	2135
				1265	2104	2111	2138	2104	2131	2107	2135	2149	2176	2154	2189	2164	2192	2134	1322
				(-511) (-511) (-511)>;

			PS_Config_Lmt_FW_Rawdata_P = <
				2052	2052	2067	2067	2072	2057	2068	2059	2077	2061	2043	2089	2041	2046	2094	2080
				2078	2035	2024	2083	2089	2024	2011	2095	2093	2046	2054	2095	2041	2047	2074	2073
				2052	2082	2046	2067	2061	2056	2065	2056	2078	2052	2041	2063	2072	2044	2070	2043
				2054	2077	2077	2046	2067	2072	2044	2048	2072	2056	2070	2069	2052	2043	2067	2038
				2055	2056	2093	2038	2090	2067	2074	2086	2081	2054	2083	2041	2067	2074	2065	2077
				2047	2087	2103	2083	2026	2115	2104	2112	2052	2102	2033	2096	2034	2102	2055	2026
				2061	2091	2016	2130	2003	2051	2009	2076	2043	1999	2098	2042	2102	2042	2064	2017
				2015	2057	2099	2054	2056	2070	2055	2068	2077	2029	2085	2050	2077	2054	2085	2078
				2018	2055	2055	2039	2082	2065	2054	2080	2061	2112	2070	2031	2069	2089	2069	2015
				2072	2059	2083	2099	2044	2052	2051	2048	2026	2085	2034	2099	2029	2087	2078	2068
				2055	2068	2056	2043	2064	2026	2065	2076	2056	2081	2046	2037	2061	2069	2052	2073
				2055	2065	2047	2060	2060	2034	2067	2069	2089	2103	2028	2025	2085	2093	2026	2063
				2044	2064	2050	2067	2038	2025	2039	2051	2063	2047	2074	2063	2060	2051	2051	2064
				2037	2057	2073	2093	2038	2034	2061	2098	2072	2089	2054	2051	2055	2044	2070	2005
				2025	2026	2076	2028	2093	2090	2031	2086	2096	2093	2061	2054	2067	2054	2069	2044
				2047	2064	2059	2060	2039	2037	2074	2081	2086	2083	2050	2022	2087	2063	2035	2042
				2050	2061	2082	2031	2065	2073	2070	2059	2035	2100	2026	2033	2103	2030	2057	2038
				2059	2064	2056	2082	2078	2082	2047	2074	2076	2059	2073	2050	2061	2085	2031	2059
				2055	2041	2077	2069	2090	2070	2029	2068	2043	2052	2067	2080	2043	2065	2055	2089
				2021	2067	2083	2048	2056	2065	2085	2042	2064	2052	2073	2081	2050	2074	2063	2063
				2056	2056	2031	2085	2035	2056	2061	2061	2039	2061	2050	2046	2063	2052	2076	2025
				2054	2082	2060	2064	2056	2102	2073	2078	2061	2081	2055	2057	2065	2037	2070	2059
				2030	2057	2044	2086	2030	2029	2078	2100	2096	2018	2102	2020	2082	2099	2038	2050
				2060	2081	2037	2090	2034	2072	2089	2015	2041	2041	2072	2035	2048	2094	2047	2050
				2042	2102	2034	2046	2034	2074	2037	2052	2042	2052	2041	2063	2055	2052	2043	2037
				2013	2039	2067	2057	2067	2059	2056	2078	2074	2095	2060	2102	2069	2057	2072	2070
				2031	2080	2035	2080	2048	2072	2064	2085	2064	2082	2070	2073	2087	2082	2041	2065
				2048	2051	2052	2057	2082	2037	2067	2065	2090	2051	2077	2050	2048	2083	2044	2090
				2033	2060	2067	2070	2080	2051	2039	2096	2044	2080	2030	2077	2046	2082	2052	2046
				2047	2074	2024	2087	2041	2061	2096	2069	2059	2055	2064	2068	2082	2041	2035	2060
				2044	2093	2050	2068	2034	2050	2060	2051	2067	2096	2068	2093	2052	2035	2100	2103
				2077	2022	2070	2042	2076	2007	2022	2024	2044	2081	2043	2041	2063	2072	2034	2070
				2074	2060	2096	2050	2065	2056	2087	2041	2052	2057	2060	2078	2048	2085	2082	2059
				2076	2100	2078	2026	2113	2022	2009	2047	2061	2051	2054	2089	2103	2065	2016	2060
				2061	2044	2074	2061	2093	2061	2050	2042	2077	2086	2094	2024	2087	2030	2077	2050
				2078	2060	2018	2035	2074	2030	2078	2064	2073	2048	2038	2076	2090	2048	2068	2065
				2560 2560 2560>;

			PS_Config_Lmt_FW_Rawdata_N = <
				1105	1105	1113	1113	1115	1108	1113	1108	1118	1110	1100	1124	1099	1101	1127	1120
				1119	1096	1089	1122	1124	1089	1082	1128	1127	1101	1106	1128	1099	1102	1117	1116
				1105	1121	1101	1113	1110	1107	1112	1107	1119	1105	1099	1110	1115	1101	1115	1100
				1106	1118	1118	1101	1113	1115	1101	1103	1115	1107	1115	1114	1105	1100	1113	1097
				1106	1107	1127	1097	1125	1113	1117	1123	1120	1106	1122	1099	1113	1117	1112	1118
				1102	1124	1132	1122	1091	1138	1133	1137	1105	1131	1094	1129	1095	1131	1106	1091
				1110	1126	1085	1147	1078	1104	1082	1117	1100	1076	1129	1099	1131	1099	1111	1086
				1085	1108	1130	1106	1107	1115	1106	1113	1118	1092	1122	1103	1118	1106	1122	1119
				1087	1106	1106	1098	1121	1112	1106	1120	1110	1137	1115	1094	1114	1124	1114	1085
				1115	1108	1122	1130	1101	1105	1104	1103	1091	1122	1095	1130	1092	1124	1119	1113
				1106	1113	1107	1100	1111	1091	1112	1117	1107	1120	1101	1096	1110	1114	1105	1116
				1106	1112	1102	1109	1109	1095	1113	1114	1124	1132	1092	1090	1122	1127	1091	1110
				1101	1111	1103	1113	1097	1090	1098	1104	1110	1102	1117	1110	1109	1104	1104	1111
				1096	1108	1116	1127	1097	1095	1110	1129	1115	1124	1106	1104	1106	1101	1115	1080
				1090	1091	1117	1092	1127	1125	1094	1123	1129	1127	1110	1106	1113	1106	1114	1101
				1102	1111	1108	1109	1098	1096	1117	1120	1123	1122	1103	1089	1124	1110	1096	1099
				1103	1110	1121	1094	1112	1116	1115	1108	1096	1131	1091	1094	1132	1093	1108	1097
				1108	1111	1107	1121	1119	1121	1102	1117	1117	1108	1116	1103	1110	1122	1094	1108
				1106	1099	1118	1114	1125	1115	1092	1113	1100	1105	1113	1120	1100	1112	1106	1124
				1088	1113	1122	1103	1107	1112	1122	1099	1111	1105	1116	1120	1103	1117	1110	1110
				1107	1107	1094	1122	1096	1107	1110	1110	1098	1110	1103	1101	1110	1105	1117	1090
				1106	1121	1109	1111	1107	1131	1116	1119	1110	1120	1106	1108	1112	1096	1115	1108
				1093	1108	1101	1123	1093	1092	1119	1131	1129	1087	1131	1087	1121	1130	1097	1103
				1109	1120	1096	1125	1095	1115	1124	1085	1099	1099	1115	1096	1103	1127	1102	1103
				1099	1131	1095	1101	1095	1117	1096	1105	1099	1105	1099	1110	1106	1105	1100	1096
				1084	1098	1113	1108	1113	1108	1107	1119	1117	1128	1109	1131	1114	1108	1115	1115
				1094	1120	1096	1120	1103	1115	1111	1122	1111	1121	1115	1116	1124	1121	1099	1112
				1103	1104	1105	1108	1121	1096	1113	1112	1125	1104	1118	1103	1103	1122	1101	1125
				1094	1109	1113	1115	1120	1104	1098	1129	1101	1120	1093	1118	1101	1121	1105	1101
				1102	1117	1089	1124	1099	1110	1129	1114	1108	1106	1111	1113	1121	1099	1096	1109
				1101	1127	1103	1113	1095	1103	1109	1104	1113	1129	1113	1127	1105	1096	1131	1132
				1118	1089	1115	1099	1117	1080	1089	1089	1101	1120	1100	1099	1110	1115	1095	1115
				1117	1109	1129	1103	1112	1107	1124	1099	1105	1108	1109	1119	1103	1122	1121	1108
				1117	1131	1119	1091	1138	1089	1082	1102	1110	1104	1106	1124	1132	1112	1085	1109
				1110	1101	1117	1110	1127	1110	1103	1099	1118	1123	1127	1089	1124	1093	1118	1103
				1119	1109	1087	1096	1117	1093	1119	1111	1116	1103	1097	1117	1125	1103	1113	1112
				240 240 240>;

			PS_Config_Lmt_FW_CC_P = <
				112	125	124	122	121	120	119	65535	65535	125	122	122	122	124	124	110
				126	115	112	110	110	110	110	110	115	114	111	110	111	112	112	115
				135	112	110	109	107	107	107	107	112	112	110	107	110	110	110	115
				122	112	111	110	110	109	109	109	114	112	110	110	111	111	112	117
				119	112	111	110	109	107	107	107	112	111	110	110	110	111	112	115
				120	114	112	111	110	110	110	110	114	112	111	110	112	112	114	116
				120	111	110	109	107	107	107	107	111	111	110	109	110	111	111	116
				120	112	111	110	110	109	110	109	112	112	110	110	111	112	112	119
				117	112	111	110	109	107	109	107	112	111	110	110	110	111	112	115
				119	112	112	111	110	110	110	110	115	112	112	111	112	112	114	115
				119	110	110	109	107	106	107	107	111	110	109	109	110	110	111	116
				120	111	110	110	107	107	107	107	111	110	110	109	110	110	112	120
				116	111	110	110	107	107	107	109	110	110	110	110	110	112	112	116
				117	112	112	111	110	110	110	111	112	112	112	112	112	114	115	119
				116	110	110	107	107	107	107	110	110	110	110	110	110	111	112	117
				119	112	111	110	109	110	110	111	111	111	110	110	111	112	112	119
				115	111	110	110	107	107	109	110	112	110	110	110	111	112	112	115
				117	112	112	111	109	109	110	111	112	111	110	110	111	112	114	117
				115	111	110	109	106	107	107	109	109	109	107	107	109	110	111	117
				117	112	110	110	107	107	109	110	112	110	110	110	110	111	112	120
				115	111	110	109	109	109	109	109	111	110	109	110	110	111	112	117
				116	112	112	110	110	110	110	110	112	111	110	110	112	112	114	120
				116	110	110	107	107	107	107	109	110	110	109	109	110	110	112	119
				117	111	111	110	109	109	110	111	111	110	109	110	111	112	112	122
				115	111	110	109	107	109	109	110	110	110	109	109	111	111	112	120
				116	114	112	111	110	111	112	112	112	112	111	112	112	115	115	121
				115	111	110	109	107	109	110	111	109	110	109	110	110	111	112	121
				119	112	112	110	110	110	111	112	110	111	110	111	112	112	115	122
				115	112	111	110	109	110	111	112	110	110	110	110	112	112	114	121
				117	114	114	111	110	111	112	114	111	112	111	112	112	115	116	122
				116	111	110	109	107	109	109	111	110	110	109	110	111	112	115	122
				117	114	112	111	110	111	112	114	110	111	110	112	112	114	115	125
				115	112	110	110	109	110	111	112	110	110	110	110	112	112	115	122
				117	114	112	112	110	111	114	115	111	111	111	112	114	115	117	140
				115	112	110	110	109	109	114	112	109	109	109	110	111	112	115	115
				112	124	122	122	121	122	126	126	124	122	124	124	125	126	128	120
				314 314 314>;

			PS_Config_Lmt_FW_CC_N = <
				69	76	76	75	74	73	72	(-65535)	(-65535)	76	75	75	75	76	76	67
				77	70	69	67	67	67	67	67	70	69	68	67	68	69	69	70
				82	69	67	66	66	66	66	66	69	69	67	66	67	67	67	70
				75	69	68	67	67	66	66	66	69	69	67	67	68	68	69	72
				72	69	68	67	66	66	66	66	69	68	67	67	67	68	69	70
				73	69	69	68	67	67	67	67	69	69	68	67	69	69	69	71
				73	68	67	66	66	66	66	66	68	68	67	66	67	68	68	71
				73	69	68	67	67	66	67	66	69	69	67	67	68	69	69	72
				72	69	68	67	66	66	66	66	69	68	67	67	67	68	69	70
				72	69	69	68	67	67	67	67	70	69	69	68	69	69	69	70
				72	67	67	66	66	65	66	66	68	67	66	66	67	67	68	71
				73	68	67	67	66	66	66	66	68	67	67	66	67	67	69	73
				71	68	67	67	66	66	66	66	67	67	67	67	67	69	69	71
				72	69	69	68	67	67	67	68	69	69	69	69	69	69	70	72
				71	67	67	66	66	66	66	67	67	67	67	67	67	68	69	72
				72	69	68	67	66	67	67	68	68	68	67	67	68	69	69	72
				70	68	67	67	66	66	66	67	69	67	67	67	68	69	69	70
				72	69	69	68	66	66	67	68	69	68	67	67	68	69	69	72
				70	68	67	66	65	66	66	66	66	66	66	66	66	67	68	72
				72	69	67	67	66	66	66	67	69	67	67	67	67	68	69	73
				70	68	67	66	66	66	66	66	68	67	66	67	67	68	69	72
				71	69	69	67	67	67	67	67	69	68	67	67	69	69	69	73
				71	67	67	66	66	66	66	66	67	67	66	66	67	67	69	72
				72	68	68	67	66	66	67	68	68	67	66	67	68	69	69	75
				70	68	67	66	66	66	66	67	67	67	66	66	68	68	69	73
				71	69	69	68	67	68	69	69	69	69	68	69	69	70	70	74
				70	68	67	66	66	66	67	68	66	67	66	67	67	68	69	74
				72	69	69	67	67	67	68	69	67	68	67	68	69	69	70	75
				70	69	68	67	66	67	68	69	67	67	67	67	69	69	69	74
				72	69	69	68	67	68	69	69	68	69	68	69	69	70	71	75
				71	68	67	66	66	66	66	68	67	67	66	67	68	69	70	75
				72	69	69	68	67	68	69	69	67	68	67	69	69	69	70	76
				70	69	67	67	66	67	68	69	67	67	67	67	69	69	70	75
				72	69	69	69	67	68	69	70	68	68	68	69	69	70	72	85
				70	69	67	67	66	66	69	69	66	66	66	67	68	69	70	70
				69	76	75	75	74	75	77	77	76	75	76	76	76	77	79	73
				0 0 0>;

			PS_Config_Lmt_FW_Diff_P = <
				50	50	50	50	50	50	50	65535	65535	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				75 75 75>;

			PS_Config_Lmt_FW_Diff_N = <
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-65535)	(-65535)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-75) (-75) (-75)>;

			PS_Config_Diff_Test_Frame = <50>;
		};

		/*for Xiaomi J19 672A BOE6.53" DJN module*/
		novatek-mp-criteria-5939@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "novatek-mp-criteria-5939";

			/* MP Config */
			IC_X_CFG_SIZE = <18>;
			IC_Y_CFG_SIZE = <36>;
			IC_KEY_CFG_SIZE = <4>;
			X_Channel = <18>;
			Y_Channel = <36>;
			AIN_X = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17>;
			AIN_Y = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
						18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35>;
			AIN_KEY = <0 1 2 0xFF>;

			/* MP Criteria */
			PS_Config_Lmt_Short_Rawdata_P = <
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008>;

			PS_Config_Lmt_Short_Rawdata_N = <
				10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000
				10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000
				10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000
				10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000
				10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000
				10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000
				10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000
				10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000
				10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000
				10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000
				10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000
				10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000
				10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000
				10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000
				10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000
				10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000
				10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000
				10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000
				10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000
				10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000
				10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000
				10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000
				10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000
				10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000
				10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000
				10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000
				10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000
				10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000
				10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000
				10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000
				10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000
				10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000
				10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000
				10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000
				10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000
				10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000 10000
				10000 10000 10000>;

			PS_Config_Lmt_Open_Rawdata_P = <
				5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120
				5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120
				5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120
				5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120
				5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120
				5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120
				5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120
				5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120
				5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120
				5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120
				5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120
				5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120
				5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120
				5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120
				5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120
				5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120
				5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120
				5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120
				5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120
				5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120
				5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120
				5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120
				5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120
				5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120
				5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120
				5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120
				5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120
				5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120
				5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120
				5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120
				5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120
				5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120
				5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120
				5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120
				5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120
				5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120 5120
				5120 5120 5120>;

			PS_Config_Lmt_Open_Rawdata_N = <
				(-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511)
				(-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511)
				(-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511)
				(-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511)
				(-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511)
				(-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511)
				(-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511)
				(-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511)
				(-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511)
				(-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511)
				(-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511)
				(-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511)
				(-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511)
				(-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511)
				(-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511)
				(-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511)
				(-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511)
				(-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511)
				(-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511)
				(-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511)
				(-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511)
				(-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511)
				(-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511)
				(-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511)
				(-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511)
				(-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511)
				(-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511)
				(-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511)
				(-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511)
				(-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511)
				(-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511)
				(-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511)
				(-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511)
				(-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511)
				(-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511)
				(-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511) (-511)
				(-511) (-511) (-511)>;

			PS_Config_Lmt_FW_Rawdata_P = <
				2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560
				2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560
				2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560
				2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560
				2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560
				2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560
				2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560
				2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560
				2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560
				2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560
				2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560
				2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560
				2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560
				2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560
				2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560
				2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560
				2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560
				2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560
				2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560
				2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560
				2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560
				2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560
				2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560
				2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560
				2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560
				2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560
				2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560
				2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560
				2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560
				2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560
				2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560
				2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560
				2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560
				2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560
				2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560
				2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560 2560
				2560 2560 2560>;

			PS_Config_Lmt_FW_Rawdata_N = <
				240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240
				240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240
				240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240
				240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240
				240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240
				240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240
				240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240
				240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240
				240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240
				240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240
				240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240
				240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240
				240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240
				240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240
				240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240
				240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240
				240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240
				240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240
				240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240
				240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240
				240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240
				240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240
				240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240
				240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240
				240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240
				240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240
				240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240
				240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240
				240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240
				240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240
				240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240
				240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240
				240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240
				240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240
				240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240
				240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240 240
				240 240 240>;

			PS_Config_Lmt_FW_CC_P = <
				314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314
				314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314
				314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314
				314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314
				314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314
				314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314
				314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314
				314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314
				314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314
				314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314
				314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314
				314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314
				314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314
				314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314
				314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314
				314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314
				314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314
				314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314
				314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314
				314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314
				314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314
				314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314
				314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314
				314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314
				314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314
				314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314
				314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314
				314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314
				314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314
				314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314
				314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314
				314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314
				314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314
				314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314
				314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314
				314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314 314
				314 314 314>;

			PS_Config_Lmt_FW_CC_N = <
				0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
				0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
				0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
				0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
				0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
				0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
				0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
				0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
				0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
				0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
				0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
				0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
				0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
				0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
				0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
				0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
				0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
				0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
				0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
				0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
				0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
				0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
				0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
				0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
				0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
				0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
				0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
				0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
				0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
				0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
				0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
				0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
				0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
				0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
				0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
				0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
				0 0 0>;

			PS_Config_Lmt_FW_Diff_P = <
				75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
				75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
				75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
				75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
				75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
				75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
				75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
				75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
				75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
				75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
				75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
				75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
				75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
				75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
				75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
				75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
				75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
				75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
				75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
				75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
				75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
				75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
				75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
				75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
				75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
				75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
				75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
				75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
				75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
				75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
				75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
				75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
				75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
				75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
				75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
				75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75
				75 75 75>;

			PS_Config_Lmt_FW_Diff_N = <
				(-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75)
				(-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75)
				(-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75)
				(-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75)
				(-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75)
				(-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75)
				(-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75)
				(-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75)
				(-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75)
				(-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75)
				(-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75)
				(-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75)
				(-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75)
				(-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75)
				(-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75)
				(-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75)
				(-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75)
				(-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75)
				(-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75)
				(-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75)
				(-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75)
				(-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75)
				(-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75)
				(-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75)
				(-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75)
				(-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75)
				(-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75)
				(-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75)
				(-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75)
				(-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75)
				(-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75)
				(-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75)
				(-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75)
				(-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75)
				(-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75)
				(-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75) (-75)
				(-75) (-75) (-75)>;

			PS_Config_Diff_Test_Frame = <50>;
		};
/*for Xiaomi J19 672D BOE6.53" DJN module*/
		novatek-mp-criteria-5944@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "novatek-mp-criteria-5944";

			/* MP Config */
			IC_X_CFG_SIZE = <18>;
			IC_Y_CFG_SIZE = <36>;
			IC_KEY_CFG_SIZE = <4>;
			X_Channel = <18>;
			Y_Channel = <36>;
			AIN_X = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17>;
			AIN_Y = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
						18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35>;
			AIN_KEY = <0 1 2 0xFF>;

			/* MP Criteria */
			PS_Config_Lmt_Short_Rawdata_P = <
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008 14008
				14008 14008 14008>;

			PS_Config_Lmt_Short_Rawdata_N = <
				10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100
				10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100
				10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100
				10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100
				10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100
				10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100
				10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100
				10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100
				10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100
				10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100
				10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100
				10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100
				10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100
				10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100
				10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100
				10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100
				10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100
				10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100
				10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100
				10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100
				10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100
				10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100
				10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100
				10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100
				10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100
				10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100
				10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100
				10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100
				10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100
				10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100
				10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100
				10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100
				10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100
				10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100
				10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100
				10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100 10100
				10000 10000 10000>;

			PS_Config_Lmt_Open_Rawdata_P = <
				3279	3431	3560	3650	3693	3720	3756	3672	65535	65535	3620	3696	3665	3633	3599	3546	3445	3289
				3220	3506	3613	3720	3769	3801	3854	3482	3938	3800	3374	3711	3682	3651	3625	3580	3525	3247
				3259	3520	3598	3688	3731	3756	3795	3826	3893	3762	3731	3700	3667	3633	3598	3550	3490	3240
				3420	3520	3618	3730	3787	3825	3865	3913	3952	3767	3738	3713	3686	3653	3622	3583	3524	3485
				3448	3496	3590	3674	3725	3762	3795	3830	3892	3794	3763	3730	3683	3653	3613	3557	3508	3465
				3518	3576	3682	3780	3846	3888	3926	3965	4003	3871	3791	3765	3728	3711	3685	3646	3612	3570
				3511	3548	3637	3718	3780	3804	3840	3870	3944	3829	3788	3758	3728	3700	3667	3616	3576	3528
				3536	3543	3681	3783	3857	3892	3938	3973	4017	3885	3758	3759	3735	3709	3689	3648	3623	3585
				3517	3563	3636	3730	3793	3822	3853	3893	3961	3821	3779	3742	3704	3675	3643	3598	3552	3517
				3543	3606	3690	3801	3878	3921	3963	4008	4036	3871	3791	3760	3730	3704	3675	3639	3597	3571
				3531	3573	3611	3730	3809	3844	3874	3906	3970	3835	3797	3717	3716	3685	3651	3598	3555	3525
				3588	3647	3727	3819	3909	3948	3983	4017	4047	3919	3839	3801	3767	3752	3725	3688	3654	3633
				3602	3644	3709	3783	3861	3892	3926	3948	4008	3844	3811	3767	3734	3697	3667	3630	3588	3567
				3609	3671	3749	3829	3927	3965	4012	4046	4073	3902	3840	3797	3758	3730	3707	3682	3657	3636
				3623	3675	3730	3762	3879	3912	3945	3972	4017	3833	3805	3769	3681	3679	3653	3619	3580	3562
				3588	3658	3728	3814	3906	3949	3998	4032	4049	3860	3811	3784	3723	3689	3665	3637	3606	3595
				3560	3529	3563	3601	3623	3665	3710	3744	3780	3979	3930	3892	3829	3793	3703	3619	3536	3471
				3618	3598	3640	3693	3710	3774	3825	3864	3903	3983	3940	3912	3857	3816	3753	3682	3609	3611
				3605	3577	3611	3637	3633	3679	3724	3753	3783	3921	3884	3847	3800	3752	3692	3611	3548	3542
				3611	3591	3643	3685	3713	3745	3797	3825	3864	3969	3931	3902	3853	3823	3752	3678	3612	3611
				3602	3578	3608	3640	3660	3674	3720	3745	3779	3907	3865	3840	3795	3760	3682	3616	3542	3538
				3571	3559	3608	3662	3695	3685	3773	3807	3846	3906	3874	3844	3801	3763	3662	3630	3556	3560
				3531	3518	3559	3590	3613	3633	3675	3707	3738	3870	3828	3800	3742	3710	3634	3557	3482	3480
				3576	3577	3623	3669	3700	3725	3766	3802	3843	3900	3857	3832	3779	3753	3685	3616	3546	3556
				3552	3545	3584	3609	3632	3640	3678	3700	3734	3861	3819	3787	3738	3706	3647	3562	3499	3492
				3549	3553	3606	3646	3679	3693	3710	3766	3812	3867	3826	3795	3752	3720	3671	3563	3531	3527
				3499	3506	3541	3577	3594	3604	3634	3654	3692	3795	3758	3732	3686	3653	3599	3520	3448	3441
				3499	3510	3563	3616	3646	3661	3706	3731	3772	3816	3776	3751	3707	3672	3629	3556	3478	3478
				3447	3455	3499	3528	3546	3564	3595	3587	3650	3749	3711	3688	3630	3599	3553	3466	3370	3385
				3471	3492	3555	3595	3625	3648	3681	3696	3739	3791	3745	3727	3679	3655	3619	3541	3464	3465
				3420	3426	3480	3503	3524	3536	3569	3576	3618	3716	3682	3654	3609	3577	3542	3461	3385	3366
				3440	3461	3531	3569	3595	3612	3651	3664	3697	3716	3671	3646	3605	3581	3557	3482	3415	3395
				3367	3387	3441	3472	3492	3507	3539	3552	3571	3641	3612	3590	3543	3515	3482	3413	3332	3282
				3032	3378	3450	3501	3532	3553	3595	3620	3644	3647	3598	3578	3532	3500	3471	3410	3332	2996
				3011	3303	3368	3427	3448	3472	3499	3513	3549	3569	3538	3511	3461	3427	3392	3342	3272	2971
				3108	3286	3413	3483	3514	3548	3581	3609	3639	3620	3562	3535	3487	3465	3433	3394	3283	3111
				5120 5120 5120>;

			PS_Config_Lmt_Open_Rawdata_N = <
				1309	1355	1403	1440	1459	1469	1486	1465	(-65535)	(-65535)	1451	1470	1451	1432	1412	1385	1346	1297
				1288	1378	1421	1464	1484	1497	1519	1392	1565	1519	1355	1469	1456	1444	1432	1412	1388	1301
				1319	1403	1437	1474	1490	1497	1512	1525	1556	1502	1487	1471	1452	1436	1420	1399	1372	1294
				1359	1394	1433	1481	1505	1521	1540	1562	1581	1496	1475	1459	1443	1428	1415	1399	1373	1361
				1366	1384	1421	1456	1477	1490	1505	1519	1549	1511	1497	1481	1462	1450	1435	1411	1388	1374
				1394	1416	1460	1500	1528	1545	1563	1583	1602	1541	1506	1492	1475	1466	1453	1433	1419	1405
				1388	1401	1439	1473	1500	1508	1525	1540	1576	1525	1508	1495	1484	1471	1454	1430	1411	1396
				1399	1405	1459	1501	1535	1551	1572	1588	1608	1552	1502	1500	1490	1477	1466	1447	1436	1423
				1413	1429	1459	1498	1524	1537	1549	1567	1597	1528	1511	1495	1479	1468	1454	1436	1417	1406
				1418	1440	1475	1522	1554	1571	1588	1609	1622	1553	1519	1505	1491	1481	1469	1456	1436	1430
				1409	1423	1444	1493	1528	1541	1556	1571	1603	1543	1529	1498	1494	1482	1465	1439	1418	1411
				1428	1448	1485	1526	1568	1588	1603	1619	1635	1565	1530	1513	1498	1491	1481	1465	1452	1450
				1429	1443	1472	1504	1538	1549	1564	1573	1603	1542	1529	1511	1496	1481	1466	1448	1430	1424
				1439	1462	1497	1534	1578	1594	1614	1628	1641	1565	1539	1521	1502	1487	1475	1461	1446	1443
				1455	1473	1496	1514	1562	1575	1590	1601	1622	1553	1541	1525	1492	1490	1478	1461	1446	1448
				1445	1471	1501	1539	1580	1600	1625	1642	1651	1564	1543	1529	1502	1486	1472	1457	1447	1451
				1443	1418	1433	1448	1459	1475	1496	1513	1532	1624	1603	1585	1558	1541	1498	1459	1422	1411
				1460	1439	1457	1481	1492	1516	1537	1556	1576	1634	1614	1602	1577	1559	1527	1493	1460	1471
				1467	1444	1460	1473	1475	1492	1510	1522	1538	1610	1592	1576	1553	1532	1501	1464	1436	1445
				1466	1448	1470	1487	1499	1513	1538	1550	1567	1624	1608	1593	1571	1559	1526	1493	1465	1475
				1469	1446	1459	1474	1484	1492	1513	1524	1538	1604	1585	1572	1553	1538	1501	1470	1435	1444
				1456	1440	1461	1483	1496	1495	1531	1545	1564	1606	1591	1579	1560	1546	1503	1484	1449	1461
				1461	1445	1463	1476	1486	1492	1509	1522	1536	1592	1574	1561	1538	1526	1492	1456	1421	1432
				1469	1457	1477	1498	1513	1525	1546	1563	1583	1609	1593	1586	1561	1550	1519	1487	1456	1471
				1467	1452	1471	1484	1493	1498	1514	1523	1539	1598	1580	1563	1538	1524	1496	1456	1425	1435
				1464	1452	1475	1491	1507	1514	1526	1549	1571	1595	1576	1563	1542	1527	1505	1462	1444	1455
				1462	1451	1465	1479	1484	1487	1499	1508	1526	1579	1561	1550	1530	1516	1493	1457	1426	1435
				1450	1442	1462	1487	1502	1513	1535	1546	1566	1592	1574	1562	1542	1526	1508	1473	1436	1449
				1441	1430	1450	1465	1475	1484	1500	1499	1528	1561	1544	1534	1510	1497	1477	1438	1396	1414
				1454	1451	1477	1495	1508	1519	1534	1541	1561	1581	1562	1554	1535	1525	1508	1469	1433	1445
				1455	1444	1469	1478	1488	1492	1505	1509	1529	1549	1534	1525	1507	1495	1483	1447	1414	1418
				1442	1438	1469	1486	1499	1506	1524	1531	1544	1560	1538	1527	1510	1501	1493	1459	1429	1435
				1431	1426	1451	1463	1472	1476	1490	1497	1509	1522	1508	1499	1480	1468	1453	1426	1390	1384
				1288	1414	1447	1471	1484	1495	1514	1526	1538	1532	1510	1501	1483	1472	1461	1435	1402	1278
				1286	1392	1421	1446	1456	1466	1478	1484	1500	1508	1495	1483	1462	1450	1435	1412	1379	1268
				1337	1406	1463	1496	1511	1525	1541	1553	1568	1542	1517	1507	1488	1480	1465	1447	1396	1328
				(-511) (-511) (-511)>;

			PS_Config_Lmt_FW_Rawdata_P = <
				1064	1141	1132	1090	1143	1100	1106	1128	65535	65535	1085	1090	1096	1111	1071	1093	1078	1078
				1093	1118	1107	1132	1114	1124	1103	1110	1100	1118	1096	1092	1104	1092	1100	1100	1100	1129
				1107	1134	1134	1128	1128	1120	1134	1124	1100	1120	1096	1125	1115	1110	1108	1096	1097	1117
				1100	1097	1080	1093	1104	1108	1111	1134	1110	1118	1125	1120	1122	1107	1113	1121	1132	1092
				1089	1134	1152	1157	1143	1142	1149	1138	1086	1113	1138	1099	1106	1132	1104	1115	1099	1139
				1114	1127	1139	1134	1124	1134	1142	1099	1141	1113	1127	1106	1127	1096	1125	1108	1097	1106
				1110	1115	1115	1107	1103	1096	1103	1100	1117	1121	1106	1111	1092	1134	1114	1110	1114	1114
				1087	1093	1089	1096	1104	1103	1097	1108	1100	1120	1124	1129	1121	1104	1122	1122	1120	1108
				1089	1117	1135	1110	1129	1118	1143	1085	1124	1120	1131	1120	1108	1097	1114	1110	1127	1128
				1134	1082	1083	1087	1075	1110	1092	1136	1096	1092	1100	1065	1082	1069	1079	1090	1085	1118
				1138	1087	1092	1086	1083	1104	1093	1135	1101	1120	1125	1122	1117	1113	1128	1131	1138	1120
				1092	1134	1135	1146	1135	1157	1141	1093	1149	1110	1087	1087	1085	1099	1090	1099	1103	1139
				1103	1143	1141	1115	1149	1101	1099	1103	1131	1101	1131	1071	1068	1062	1066	1059	1051	1141
				1118	1125	1141	1118	1132	1128	1136	1104	1136	1114	1121	1106	1101	1094	1104	1087	1083	1160
				1090	1152	1153	1131	1132	1066	1066	1073	1129	1101	1122	1111	1117	1125	1124	1107	1090	1107
				1148	1101	1090	1120	1107	1080	1097	1120	1148	1114	1113	1118	1115	1094	1099	1113	1118	1100
				1099	1101	1092	1082	1094	1110	1113	1103	1099	1107	1103	1092	1106	1099	1107	1089	1104	1107
				1113	1107	1113	1118	1106	1113	1115	1110	1093	1115	1107	1104	1104	1108	1114	1111	1087	1132
				1089	1146	1135	1135	1125	1122	1145	1127	1143	1145	1111	1122	1103	1086	1107	1092	1111	1108
				1092	1122	1121	1124	1104	1108	1118	1115	1150	1117	1125	1120	1101	1118	1128	1118	1120	1111
				1087	1143	1124	1135	1128	1134	1125	1127	1097	1073	1122	1092	1159	1178	1157	1169	1155	1125
				1092	1083	1090	1092	1086	1099	1101	1100	1111	1129	1128	1121	1111	1115	1118	1113	1128	1085
				1125	1115	1125	1135	1124	1139	1129	1142	1145	1108	1111	1115	1125	1131	1120	1121	1128	1111
				1145	1117	1142	1135	1143	1141	1108	1099	1101	1127	1104	1100	1122	1103	1100	1100	1083	1142
				1129	1104	1101	1110	1131	1128	1113	1117	1142	1113	1128	1132	1110	1107	1106	1097	1101	1103
				1113	1149	1139	1135	1136	1134	1138	1156	1135	1139	1094	1103	1128	1127	1121	1138	1121	1121
				1120	1106	1117	1136	1100	1139	1090	1101	1101	1103	1097	1104	1108	1103	1106	1113	1125	1106
				1131	1110	1114	1135	1138	1128	1134	1127	1120	1122	1106	1113	1094	1107	1093	1093	1099	1120
				1115	1103	1057	1157	1155	1149	1135	1152	1122	1087	1107	1104	1103	1107	1106	1117	1108	1100
				1163	1075	1059	1132	1072	1148	1103	1124	1068	1092	1124	1127	1107	1121	1115	1121	1115	1092
				1124	1107	1103	1115	1114	1118	1121	1128	1122	1127	1117	1106	1127	1122	1128	1113	1103	1099
				1107	1114	1127	1117	1117	1111	1114	1113	1122	1106	1078	1083	1075	1076	1082	1127	1083	1114
				1106	1143	1097	1156	1145	1148	1118	1143	1131	1120	1096	1131	1118	1103	1118	1122	1128	1134
				1080	1120	1129	1114	1128	1110	1118	1115	1113	1122	1120	1078	1120	1127	1127	1073	1092	1092
				1113	1108	1111	1135	1142	1136	1135	1146	1132	1097	1142	1092	1087	1111	1104	1121	1117	1094
				1121	1092	1096	1086	1092	1076	1101	1128	1122	1117	1106	1121	1128	1108	1100	1075	1099	1113
				2560 2560 2560>;

			PS_Config_Lmt_FW_Rawdata_N = <
				456	489	485	467	490	471	474	483	(-65535)	(-65535)	465	467	469	476	459	468	462	462
				468	479	474	485	477	481	472	475	471	479	469	468	473	468	471	471	471	484
				474	486	486	483	483	480	486	481	471	480	469	482	478	475	475	469	470	478
				471	470	463	468	473	475	476	486	475	479	482	480	481	474	477	480	485	468
				466	486	493	496	490	489	492	487	465	477	487	471	474	485	473	478	471	488
				477	483	488	486	481	486	489	471	489	477	483	474	483	469	482	475	470	474
				475	478	478	474	472	469	472	471	478	480	474	476	468	486	477	475	477	477
				466	468	466	469	473	472	470	475	471	480	481	484	480	473	481	481	480	475
				466	478	486	475	484	479	490	465	481	480	484	480	475	470	477	475	483	483
				486	463	464	466	460	475	468	487	469	468	471	456	463	458	462	467	465	479
				487	466	468	465	464	473	468	486	472	480	482	481	478	477	483	484	487	480
				468	486	486	491	486	496	489	468	492	475	466	466	465	471	467	471	472	488
				472	490	489	478	492	472	471	472	484	472	484	459	457	455	457	454	450	489
				479	482	489	479	485	483	487	473	487	477	480	474	472	469	473	466	464	497
				467	493	494	484	485	457	457	460	484	472	481	476	478	482	481	474	467	474
				492	472	467	480	474	463	470	480	492	477	477	479	478	469	471	477	479	471
				471	472	468	463	469	475	477	472	471	474	472	468	474	471	474	466	473	474
				477	474	477	479	474	477	478	475	468	478	474	473	473	475	477	476	466	485
				466	491	486	486	482	481	490	483	490	490	476	481	472	465	474	468	476	475
				468	481	480	481	473	475	479	478	493	478	482	480	472	479	483	479	480	476
				466	490	481	486	483	486	482	483	470	460	481	468	496	505	496	501	495	482
				468	464	467	468	465	471	472	471	476	484	483	480	476	478	479	477	483	465
				482	478	482	486	481	488	484	489	490	475	476	478	482	484	480	480	483	476
				490	478	489	486	490	489	475	471	472	483	473	471	481	472	471	471	464	489
				484	473	472	475	484	483	477	478	489	477	483	485	475	474	474	470	472	472
				477	492	488	486	487	486	487	495	486	488	469	472	483	483	480	487	480	480
				480	474	478	487	471	488	467	472	472	472	470	473	475	472	474	477	482	474
				484	475	477	486	487	483	486	483	480	481	474	477	469	474	468	468	471	480
				478	472	453	496	495	492	486	493	481	466	474	473	472	474	474	478	475	471
				498	460	454	485	459	492	472	481	457	468	481	483	474	480	478	480	478	468
				481	474	472	478	477	479	480	483	481	483	478	474	483	481	483	477	472	471
				474	477	483	478	478	476	477	477	481	474	462	464	460	461	463	483	464	477
				474	490	470	495	490	492	479	490	484	480	469	484	479	472	479	481	483	486
				463	480	484	477	483	475	479	478	477	481	480	462	480	483	483	460	468	468
				477	475	476	486	489	487	486	491	485	470	489	468	466	476	473	480	478	469
				480	468	469	465	468	461	472	483	481	478	474	480	483	475	471	460	471	477
				240 240 240>;

			PS_Config_Lmt_FW_CC_P = <
				34	34	34	34	34	34	34	34	65535	65535	34	34	34	34	34	34	34	34
				34	33	34	33	33	34	34	34	35	35	34	34	34	34	34	34	34	34
				34	33	33	33	33	34	33	34	34	34	34	33	33	33	33	33	33	34
				34	33	34	34	33	34	34	34	34	34	33	33	33	33	33	33	33	34
				34	33	33	33	33	33	33	33	34	34	34	33	34	33	33	33	33	34
				34	34	34	34	34	34	34	34	35	34	34	34	34	34	34	34	34	34
				34	33	33	34	33	34	34	34	34	34	34	33	34	33	33	33	34	34
				34	34	34	34	33	34	34	34	35	34	34	34	34	34	34	34	34	34
				34	34	33	33	33	34	33	34	34	35	34	34	34	33	33	33	34	34
				34	34	34	34	34	34	34	34	35	34	34	34	34	34	34	34	34	34
				34	34	33	34	33	34	34	34	34	34	34	33	33	33	33	33	33	34
				34	33	33	33	33	34	34	34	35	34	34	34	34	33	34	33	33	34
				34	33	33	33	33	34	34	34	34	35	34	34	34	33	34	34	34	34
				34	34	34	34	33	34	34	34	35	35	34	34	34	33	34	34	34	34
				34	33	33	33	33	34	34	34	34	35	34	34	34	33	33	33	33	34
				34	33	34	34	34	34	34	34	35	35	34	34	34	34	34	33	33	34
				34	33	33	33	33	33	33	33	33	34	33	33	33	33	33	33	33	34
				34	34	34	34	34	34	34	34	34	34	34	34	34	33	33	33	34	34
				34	33	33	33	33	33	33	33	33	34	33	33	33	33	33	33	33	34
				34	34	33	33	33	33	34	34	34	34	34	34	33	33	34	34	34	34
				34	33	33	33	33	33	33	33	33	34	33	33	33	33	33	33	33	34
				34	34	33	33	33	33	34	34	34	34	33	33	33	33	33	33	33	34
				34	34	33	33	33	33	33	33	34	34	33	33	33	33	33	33	33	34
				34	34	33	33	33	33	33	34	34	34	34	34	33	33	34	34	34	34
				34	33	33	33	33	33	33	33	34	34	33	33	33	33	33	33	33	34
				34	33	33	33	33	33	33	33	34	34	33	33	33	33	33	33	33	34
				34	33	33	33	33	33	33	33	34	34	33	33	33	33	33	33	33	34
				34	33	33	33	33	33	33	33	34	34	33	34	33	33	33	34	34	34
				34	33	33	33	33	33	33	33	34	34	33	33	33	33	33	33	33	34
				34	33	34	33	34	33	33	33	35	34	33	33	33	34	33	34	33	34
				34	33	33	33	33	33	33	33	34	34	33	33	33	33	33	33	33	34
				34	33	33	33	33	33	33	33	34	34	33	34	33	33	33	34	34	34
				34	33	33	33	33	33	33	33	34	34	33	33	33	33	33	33	33	34
				34	33	34	33	34	33	34	34	35	34	33	33	33	33	33	34	33	34
				34	33	33	33	33	33	33	33	34	34	33	33	33	33	33	33	33	34
				34	34	34	33	34	34	34	34	35	34	33	33	33	33	33	34	34	34
				314 314 314>;

			PS_Config_Lmt_FW_CC_N = <
				15	15	15	15	15	15	15	15	(-65535)	(-65535)	15	15	15	15	15	15	15	15
				15	14	15	14	14	15	15	15	16	16	15	15	15	15	15	15	15	15
				15	14	14	14	14	15	14	15	15	15	15	14	14	14	14	14	14	15
				15	14	15	15	14	15	15	15	15	15	14	14	14	14	14	14	14	15
				15	14	14	14	14	14	14	14	15	15	15	14	15	14	14	14	14	15
				15	15	15	15	15	15	15	15	16	15	15	15	15	15	15	15	15	15
				15	14	14	15	14	15	15	15	15	15	15	14	15	14	14	14	15	15
				15	15	15	15	14	15	15	15	16	15	15	15	15	15	15	15	15	15
				15	15	14	14	14	15	14	15	15	16	15	15	15	14	14	14	15	15
				15	15	15	15	15	15	15	15	16	15	15	15	15	15	15	15	15	15
				15	15	14	15	14	15	15	15	15	15	15	14	14	14	14	14	14	15
				15	14	14	14	14	15	15	15	16	15	15	15	15	14	15	14	14	15
				15	14	14	14	14	15	15	15	15	16	15	15	15	14	15	15	15	15
				15	15	15	15	14	15	15	15	16	16	15	15	15	14	15	15	15	15
				15	14	14	14	14	15	15	15	15	16	15	15	15	14	14	14	14	15
				15	14	15	15	15	15	15	15	16	16	15	15	15	15	15	14	14	15
				15	14	14	14	14	14	14	14	14	15	14	14	14	14	14	14	14	15
				15	15	15	15	15	15	15	15	15	15	15	15	15	14	14	14	15	15
				15	14	14	14	14	14	14	14	14	15	14	14	14	14	14	14	14	15
				15	15	14	14	14	14	15	15	15	15	15	15	14	14	15	15	15	15
				15	14	14	14	14	14	14	14	14	15	14	14	14	14	14	14	14	15
				15	15	14	14	14	14	15	15	15	15	14	14	14	14	14	14	14	15
				15	15	14	14	14	14	14	14	15	15	14	14	14	14	14	14	14	15
				15	15	14	14	14	14	14	15	15	15	15	15	14	14	15	15	15	15
				15	14	14	14	14	14	14	14	15	15	14	14	14	14	14	14	14	15
				15	14	14	14	14	14	14	14	15	15	14	14	14	14	14	14	14	15
				15	14	14	14	14	14	14	14	15	15	14	14	14	14	14	14	14	15
				15	14	14	14	14	14	14	14	15	15	14	15	14	14	14	15	15	15
				15	14	14	14	14	14	14	14	15	15	14	14	14	14	14	14	14	15
				15	14	15	14	15	14	14	14	16	15	14	14	14	15	14	15	14	15
				15	14	14	14	14	14	14	14	15	15	14	14	14	14	14	14	14	15
				15	14	14	14	14	14	14	14	15	15	14	15	14	14	14	15	15	15
				15	14	14	14	14	14	14	14	15	15	14	14	14	14	14	14	14	15
				15	14	15	14	15	14	15	15	16	15	14	14	14	14	14	15	14	15
				15	14	14	14	14	14	14	14	15	15	14	14	14	14	14	14	14	15
				15	15	15	14	15	15	15	15	16	15	14	14	14	14	14	15	15	15
				0 0 0>;

			PS_Config_Lmt_FW_Diff_P = <
				50	50	50	50	50	50	50	50	65535	65535	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50	50
				75 75 75>;

			PS_Config_Lmt_FW_Diff_N = <
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-65535)	(-65535)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)	(-50)
				(-75) (-75) (-75)>;

			PS_Config_Diff_Test_Frame = <50>;
		};

	};

	/*
	focaltech@0 {
			compatible = "focaltech8719P,FTS-ts-spi";
			reg = <0>;
			spi-max-frequency = <8000000>;
			interrupt-parent = <&pio>;
			interrupts = <1 0x2>;
			focaltech,reset-gpio = <&pio 92 0x00>;
			focaltech,irq-gpio = <&pio 1 0x2001>;
			focaltech,max-touch-number = <10>;
			focaltech,display-coords =  <0 0 1080 2340>;
		};
	*/
};
#endif


#include "mediatek/mt6358.dtsi"
#include "mediatek/cust_mt6768_msdc.dtsi"
#include "mediatek/mt6370.dtsi"
#include "mediatek/mt6370_pd.dtsi"
#ifdef CONFIG_CHARGER_RT9471
#include "mediatek/rt9471.dtsi"
#endif
#ifdef CONFIG_TCPC_RT1711H
#include "mediatek/tcpc_config.dtsi"
#endif
#ifdef CONFIG_MTK_ENABLE_GENIEZONE
#include "mediatek/trusty.dtsi"
#endif
